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1 introduction preliminary programmable peripheral psd813fn/fh field-programmable microcontroller peripherals with flash memory and embedded micro ? cells tm key features the PSD813FH and psd813fn devices are field-programmable microcontroller (mcu) peripherals with flash memory. these multi-chip modules (mcm) are the first two members of a complete family of in-system-programmable (isp) peripherals from wsi that enhance any embedded microcontroller design. these devices will interface easily with most popular mcus and enable a simple two-chip solution that addresses virtually all of the mcus external needs. major features provided by the PSD813FH/fn are large flash memory, concurrent otp boot memory, battery backed sram, programmable i/o, programmable logic, address space expansion, power management, code security, and small package size. a two-chip solution consisting of an mcu and a psd813fn/fh reduces design and manufacturing cost, reduces board space, lowers power consumption, and shortens time-to-market while increasing design flexibility. in addition, in-system features such as concurrent flash read and write capability, dynamically reconfigurable i/o ports, and low power management increases system performance and manufacturing flexibility. new innovative ?icrocontroller-macrocells , called micro ? cells tm , bring inexpensive programmable logic to mcu-based embedded system designs. because the micro ? cells are directly connected to the mcu address/data bus, their programmable logic is tightly coupled to the mcu software with no hardware overhead. the mcus ability to communicate directly with the micro ? cells at the flip-flop level makes psd813fn/fh devices ideal for popular functions such as counters, serial channels, and mailboxes. when compared to industry standard cpld implementation, this architecture can save 25% to 50% of the cpld product term and macrocell resources. the psd813fn/fh devices are the first of wsis flash psd8xxf product family. starting with the psd813fn/fh, a pin-for-pin upgrade path exists for future lower cost monolithic psd8xxf devices that will incorporate expanded flash-based programmable logic, flash and eeprom memory types, larger sram, and serial isp using the industry standard jtag protocol. o mcm 5-volt only flash programmable peripheral for microcontroller-based applications o solves problems of in-system flash erase and programming concurrently operating main memory and boot memory resolves microcontroller decoding issues during flash update o two separate non-volatile memory arrays. both 1 mbit (128 kbytes) of flash memory and 256 kbits (32 kbytes) of separate otp boot eprom memory are available. the boot memory allows continuous operation of the mcu while the flash memory is being written or erased. the flash memory is divided into eight 16 kbyte sectors that can be mapped to different address spaces. access time is 150 ns which includes address latching and dpld decoding. o embedded on-chip erase and program algorithms for the flash memory. automatically accommodates on-chip events for writing and erasing the flash memory. the flash memory is byte-programmable and can be erased sector by sector or by entire chip. the embedded algorithms indicate completion of program or erase cycles by using two popular methods: data polling or bit toggling. psd813fn/fh algorithms are compatible with the standard jedec single-power-supply flash command set. return to main menu
psd813fn/fh preliminary 2 o low v cc write inhibit <= 3.2 v for the flash memory. o guaranteed minimum 10,000 erase/write cycles. o a simple, programmable interface to 8-bit microcontrollers using either multiplexed or non-multiplexed busses. the bus interface logic directly decodes microcontroller control signals. supports all popular microcontrollers. o three flexible otp pld sections one pld is used for internal psd address decoding, one is used for external device address decoding, and one is used as a general-purpose design resource. the general-purpose pld may be used to efficiently implement a variety of logic functions commonly associated with mcus such as state machines, address decoders, address generators, serial channels, multiprocessor mailboxes, and shift registers. the general-purpose pld also supports 12-output micro ? cells and 23-input micro ? cells. the mcm psd813fn/fh dedicates seven output and eight input micro ? cells to flash memory usage and sram standby voltage control. although the seven output micro ? cells are dedicated, an internal product term allocator redistributes any unused product terms if needed by the remaining micro ? cells. o internal 4kbit sram. the sram retains data if power is lost by automatically switching to an external standby power source. o nineteen individually configurable i/o port pins. the ports may be used as microcontroller i/os, pld i/os, latched microcontroller address outputs or special function i/os. o the programmable power management unit (pmu) supports two separate, low-power modes allowing operations with as little as 25? (at 5v v cc ). the device can automatically detect a lack of microcontroller activity and put the psd into power down mode. o page logic page logic is connected to the zplds and enables address space expansion for microcontrollers with limited address space capability. up to 16 pages are available. o security bit the security bit prevents reading the psd configuration, zpld, eprom boot array, and flash memory contents. this inhibits copying the device on a programmer. o development tools supported by the psdsoft tm ms-windows compatible development tools. includes psdabel as the design entry method, an efficient fitter, and an address translator (see figure 2). o packaging consists of a 52 pin plastic chip carrier. key features (cont.) please refer to the revision block at the end of this document for updated information.
preliminary psd813fn/fh 3 psd813fn/fh devices consist of several major functional blocks. figure 1 shows the architecture of the psd813fn/fh device. the functions of each block are described briefly in the following sections. many of the blocks perform multiple functions, and are user configurable. plds the device contains three pld blocks each optimized for a different function as shown in table 1. the functional partitioning of the plds reduces power consumption, optimizes cost/performance and ease of design entry. the decode pld (dpld) is used to decode and generate chip selects for the psd813fn/fh internal memory, registers, and peripheral i/o mode. the external chip select pld (ecspld) is optimized to generate chip selects for devices external to the psd813fn/fh. the general purpose pld (gpld) can implement user defined logic functions. the dpld and ecspld have combinatorial outputs while the gpld has 12 output micro ? cells. seven of the port c micro ? cells are dedicated to flash memory control. the psd813fn/fh also has 23 input micro ? cells that can be configured as inputs to the pld. the plds receive their inputs from the pld input bus. i/o ports the psd813fn/fh has 19 i/o pins divided among three ports. each i/o pin can be individually configured to provide many functions. ports a, b and d can be configured as standard mcu i/o ports, pld i/o, or latched address outputs for microcontrollers using multiplexed address/data busses. psd813fn/fh architectural overview name abbreviation inputs outputs product terms decode pld dpld 63 12 13 external chip select pld ecspld 24 7 7 general pld gpld 63 12 109 table 1.
psd813fn/fh preliminary 4 page reg pmu including cmiser features vstdby i/o port programmable i/o port programmable i/o port programmable i/o port programmable mcu address/data ad0 -ad15 mcu control interface control rd, wr security feature clkin pld input bus pld input bus output micro ? cell feedback input micro ? cell & input ports direct micro ? cell output to data bus eprom sram four blocks 256 kbit eprom 4k bits battery back - up embedded algorithm command register battery back-up i/o decode external cs pld decode pld mcu address / 8-bit data / control bus 7 external chip selects peripheral i/o selects general pld chip select to i/o allocator pt alloc. micro ? cell allocator direct micro ? cells access from data bus 103 pt 6 nibble pt i/o ports pa0 pa7 pb0 pb7 pd0 pd2 pc0 pc1 pc3 pc7 12 output micro ? cells 23 input micro ? cells (port a,b,c) (pc2) 1mb flash 8 sectors (flash rdf, wrf, a14f, a16f ?a18f) figure 1. psd813fn/fh block diagram psd813fn/fh architectural overview (cont.) * port c is dedicated to flash memory and vstdby.
preliminary psd813fn/fh 5 psd813fn/fh architectural overview (cont.) microcontroller bus interface the psd813fn/fh easily interfaces with most popular eight and sixteen-bit microcontrollers with either multiplexed or non-multiplexed address/data busses. the PSD813FH is for multiplexed applications and the psd813fn is for non-multiplexed applications. the psd813fn/fh can operate with 16-bit mcus if the mcu is configured for 8-bit external data path mode. the device is configured to respond to the microcontroller control signals which are also used as inputs to the plds. memory the psd813fn/fh contains a 1 mbit flash memory, a 256 kbit boot eprom and a 4 kbit sram. the eprom space and flash memory space are divided into four and eight equally sized blocks, respectively. each block can be located in a different address space defined by the user. the access time of either memory includes the address latching and dpld decoding. the flash memory is implemented using a 4 mbit (29040) device configured as a 1 mbit memory. all the commands for the 29040 are applicable for operating as a 1 mbit flash memory. the 4 kbit sram may be used as a scratch pad memory and an extension of the microcontroller sram. the sram data is retained in the event of a system power down, provided a backup battery is connected to the vstby pin (pc2). switching from the v cc supply to standby power occurs automatically when v cc drops below vstby voltage. page register the four-bit page register expands the address range of the microcontroller by sixteen times. the paged address can be used as part of the address space to access external memory and peripherals or internal eprom, sram and i/o. power management unit the power management unit (pmu) in the psd813fn/fh enables the user to control the power consumption on selected functional blocks based on system requirements. the pmu includes an automatic power down unit (apd) that will turn off device functions due to microcontroller inactivity in one of two modes: the power down mode and sleep mode. other power saving features, such as the cmiser in the pmu, allow the eprom/sram to operate at a slower rate to conserve power.
psd813fn/fh preliminary 6 psdabel psdcompiler psdprogrammer pld description .obj file configure psd bus interface generate abel file or use design template fitter pld fitting magic pro iii programmer chip programming address translator eprom mapping psdconfiguration third party programmers program code file figure 2. psdsoft development tools development system the psd813fn/fh devices are supported by the windows-based psdsoft development system. the psdsoft design flow is shown in figure 2. the pld design entry is done using psdabel, which creates a minimized logic implementation, and provides logic simulation of the plds. the psd813fn/fh bus interface and i/o port configuration are entered in psdconfiguration. the psdcompiler, comprised of a fitter and address translator, generates an object file from the psdabel, psdconfiguration and mcu code files. the object file is then down loaded to a programmer (magicpro iii, data i/o, or other third party programmer for device programming). psd813fn/fh devices the psd813fn/fh are two unique devices. the part classifications are based on bus mode. the features of each part are listed in table 2. zpld dpld + gpld + ecspld flash boot part bus registered i/o memory sram eprom # bit inputs micro ? cells pins pmu k bit k bit k bit PSD813FH x8/mux 63 12 19 yes 1024 4 256 psd813fn x8/non-mux 63 12 19 yes 1024 4 256 table 2. psd813fn/fh product matrix note: pmu = power management unit.
preliminary psd813fn/fh 7 the following table describes the pin names and pin functions of the psd813fn/fh. pins that have multiple names and/or functions are defined by configuration. table 3. psd813fn/fh pin descriptions pin name pin type function description adio0? 3037 i/o address/data port, interface to microcontroller bus 1. input pins for multiplexed low order address/data byte. ale or as latches address a0-7 for input to plds. the psd drives data out only if read is active and one of the internal psd functional blocks is selected. a8?5 3946 i/o address port, interface to microcontroller bus 1. address a8-15 inputs. cntl0 47 i write input pin with multiple configurations. depending on the mcu interface selected, this pin can be: (wr, 1. wr ?active low write input r_w) 2. r_w ?read/write pin, low for write bus cycle 3. control signal (cntl0) input to pld cntl1 50 i read or data strobe input pin with multiple configurations. depending on the mcu interface selected, this pin can be: (rd, 1. rd ?active low read input e, ds) 2. e ?e clock input. during a write bus cycle, e is high and r/w is low during a read bus cycle, e is high and r/w is high 3. ds ?data strobe, active low 4. control signal (cntl1) input to pld cntl2 49 i read or other control input pin with multiple configurations. depending on the mcu interface selected, this pin can be: (psen) 1. psen ?program select enable, active low in code fetch bus cycle 2. control signal (cntl2) input or general input to pld reset 48 i active low input. resets i/o ports, pld micro ? cells and some of the configuration registers. must be active at power up. pa0 29 i/o port a, pa0 ?3. this port is pin configurable and has pa1 28 multiple functions: pa2 27 1. mcu i/o ?standard output or input port pa3 25 2. external chip select (ecspld) output, or input to gpld 3. latched address outputs (see table 4) 4. as data bus port (d03) in non-multiplexed bus configuration 5. peripheral i/o mode
psd813fn/fh preliminary 8 pin name pin type function description pa4 24 i/o port a, pa4 7. this port is pin configurable and has pa5 23 cmos multiple functions: pa6 22 or 1. mcu i/o ?standard output or input port pa7 21 open 2. gpld micro ? cell (mcellab) output or input drain 3. latched address outputs (see table 4) 4. as data bus port (d4 7) in non-multiplexed bus configuration 5. peripheral i/o mode pb0 7 i/o port b, pb0 3. this port is pin configurable and has pb1 6 multiple functions: pb2 5 1. mcu i/o ?standard output or input port pb3 4 2. external chip select (ecspld) output, or input to gpld 3. latched address outputs (see table 4) pb4 3 i/o port b, pb4 7. this port is pin configurable and has multiple pb5 2 cmos functions: pb6 52 or 1. mcu i/o ?standard output or input port pb7 51 open 2. gpld micro ? cell (mcellab) output or input drain 3. latched address outputs (see table 4) pc0 (wrf) 20 flash write pc1 (rdf) 19 flash read pc3 (a14f) 17 flash address a14 pc4 (a16f) 14 * flash address a16 pc5 (a17f) 13 flash address a17 pc6 (a18f) 12 flash address a18 pc7 (cfs) 11 flash select pc2 18 i port c pin pc2. (vstby) dedicated sram standby voltage input. pin should be grounded if vstby is not required. pd0 10 i/o port d pin pd0 can be configured as: (ale) 1. ale input - latches addresses on adio0 ?5 pins 2. mcu i/o 3. gpld input 4. ecspld output pd1 9 i/o port d pin pd1 can be configured as: (clkin) 1. mcu i/o 2. gpld input 3. external chip select (ecspld) output 4. clkin clock input ?clock input to the gpld micro ? cells, the apd power down counter and gpld and array table 3. psd813fn/fh pin descriptions (cont.) * these pins are reserved for internal flash memory control and should not be used as outputs.
preliminary psd813fn/fh 9 pin name pin type function description pd2 8 i/o port d pin pd2 can be configured as: (csi) 1. mcu i/o 2. gpld input 3. external (ecspld) output 4. csi input ?when low, the csi enables the psd eprom/sram. when high, the eprom/sram are disabled to conserve power v cc 15 power pins 38 gnd 1 ground pins 16 26 microcontroller port a (3:0) port a (7:4) port b (3:0) port b (7:4) 8-bit multiplexed bus address [3:0] address [7:4] address [3:0] address [7:4] 8-bit non-multiplexed n/a n/a address [3:0] address [7:4] bus table 4. i/o port latched address output assignments* table 3. psd813fn/fh pin descriptions (cont.) n/a = not applicable * refer to the i/o port section on how to enable the latched address output function.
psd813fn/fh preliminary 10 table 5 shows the offset address to the psd813fn/fh registers relative to the csiop base address. the csiop space is the 256 bytes of address that is allocated by the user to the internal psd813fn/fh registers. psd813fn/fh register description and address offset register name port a port b port c port d other* description data in 00 01 10 11 reads port pin as input, mcu i/o input mode control 02 03 selects mode between mcu i/o or address out data out 04 05 12 13 stores data for output to port pins, mcu i/o output mode direction 06 07 14 15 configures port pin as input or output drive 08 09 16 17 configures port pin between cmos, open drain and slew rate input micro ? cell 0a 0b 18 reads input micro ? cell enable out 0c 0d 1a reads the status of the output enable to the i/o port driver output 20 20 21 read ? reads output of micro ? cell micro ? cells (mcellc, mcellab) write ? loads micro ? cell flip-flops pmmr0 b0 power management register 0 pmmr1 b2 power management register 1 page e0 page register vm e2 8031/pio configuration register table 5. register address offset * other registers that are not part of the i/o ports.
preliminary psd813fn/fh 11 the psd813fn/fh functional blocks the psd813fn/fh consists of five major functional blocks: o pld block o bus interface o i/o ports o memory block o power management unit the functions of each block are described in the following sections. many of the blocks perform multiple functions, and are user configurable. plds the plds bring programmable logic functionality to the psd813fn/fh. after specifying the logic for the plds by using the psdabel tool in the psdsoft suite, the logic configuration is programmed into the device and available when power is applied. the plds (dpld, ecspld and gpld) consist of an and array. the gpld architecture includes 12 output micro ? cells in addition to the and array. there are 23 input micro ? cells that can be configured as inputs to the pld. figure 3 shows the organization of the plds. the and array is used to form product terms specified using the psdabel tool in the psdsoft development system. when the inputs used in a term are true, the output is active. the gpld input bus consists of 63 signals as shown in table 6. both the true and complement value of inputs are available to the and array. the dpld and ecspld input busses consists of fewer inputs and is a subset of the 63 inputs. input source input name number of signals mcu address bus a [15:0] 16 mcu control signals cntl [2:0] 3 reset rst 1 power down pdn 1 i/o ports inputs (input micro ? cells) pa [7:0], pb [7:0] pc [7:3], pc [1:0] 23 port d inputs pd [2:0] 3 page register pgr [3:0] 4 port a or b micro ? cell feedback mcellab.fb [7:4] 4 port c micro ? cell feedback mcellc.fb [7:0] 8 table 6. gpld inputs
psd813fn/fh preliminary 12 pld input bus 45 4 8 24 63 output micro ? cell feedback, input micro ? cell & input ports direct micro ? cell access from data bus csiop select (csiop) sram select (rs0) flash block selects (fs 0 7) external cs pld decode pld 7 external chip selects port a, b or d peripheral i/o selects (psel 0-1) general pld chip select to i/o allocator pt alloc. micro ? cell allocator direct micro ? cell access from data bus 103 pt 6 nibble pt 23 input micro ? cell (port a,b,c) 12 output micro ? cell i/o ports eprom selects (csboot 0 3) 3 port d inputs mcell ab to port a or b mcell c to port c 1 1 2 figure 3. pld block diagram plds (cont.)
preliminary psd813fn/fh 13 each of the three plds has unique characteristics suited for its applications. they are described in the following sections. decode pld the decode pld (dpld), shown in figure 4, is used to select the internal psd813fn/fh functions: flash blocks, eprom blocks, sram, registers (csiop) and the port a peripheral mode. all the select signals are active high and have one product term. the csiop is the select line for the psd813fn/fh internal registers that occupies 256 bytes of memory space. a second level decoder selects a register based on the address inputs a[7-0]. each flash memory sector has its own chip select. the 128 kbyte flash memory is partitioned into eight 16 kbyte blocks, each with its own decoded select line (fs0-fs7). the 32 kbyte otp boot memory is partitioned into four 8 kbyte blocks, each with its own decoded select line (csboot0-csboot7). psel 0 & 1 are used as inputs to port a to control the ports peripheral i/o mode operation. usually psel 0&1 are defined in term of the mcu address inputs. this mode is explained in the i/o port section. plds (cont.) input source input name number of bits mcu address bus a[15:0] 16 i/o ports pa [7:0], pb [7:0] 23 port a, b, c pc [7:3], pc [1:0] page register pgr [3:0] 4 control signal cntl1 (read) 1 reset pin rst 1 table 7. dpld inputs
psd813fn/fh preliminary 14 (inputs) (23) (4) (16) (1) read cntl1 (1) i /o ports (port a,b,c) pgr0 - pgr3 a [ 15:0 ] reset fcs0 fcs7 rs0 csiop psel0 psel1 8 flash block selects 4 boot eprom block selects ram select i/o decoder select peripheral i/o mode select csboot 3 csboot 0 figure 4. dpld logic array plds (cont.)
preliminary psd813fn/fh 15 ecspld output port a, b, or d assignments ecs0 pa0, pb0 ecs1 pa1, pb1 ecs2 pa2, pb2 ecs3 pa3, pb3 ecs4 pd0* ecs5 pd1* ecs6 pd2* table 9. ecspld output port assignments the seven ecspld outputs may be driven off the device through ports a, b, or d, as shown in table 9, via the micro ? cell allocator. port selection is specified in the psdabel file or assigned by the psdcompiler. plds (cont.) * port d has no output enable (.oe) product terms for ecs4-6 outputs. external chip select pld the external chip select pld (ecspld) provides the means to select external devices. the output buffer of the ecspld can be configured to operate in high slew rate by writing a ??to the corresponding bit in the drive register. the slew rate is a measurement of the rise and fall times of the output. a higher slew rate means a faster output response while a lower slew rate is a slower response. refer to table 25 in the i/o section for setting up the drive register. faster transitions are more likely to cause line reflections and system noise than slower rates. adjusting the slew rate allows a trade-off between greater speed and noise sensitivity. the selection should be based on the performance requirements of the system and its noise characteristics. set the corresponding bits in the drive register to ??(for normal speed) or ??(for fast drive). the default value is zero. the ecspld has 24 inputs as shown in table 8. its outputs are combinatorial, of either polarity, and have one product term each as shown in figure 5. input source input name number of bits mcu address bus a[15:0] 16 mcu control signals cntl[2:0] 3 power down signal pdn* 1 page register pgr[3:0] 4 table 8. ecspld inputs * apd output. when pdn is high, the psd813fn/fh is in power down mode
psd813fn/fh preliminary 16 plds (cont.) (inputs) (4) (16) (3) (1) a [ 15:0 ] pgr [ 3:0 ] cntrl [ 2:0 ] , read/write control signals pdn apd output polarity bit polarity bit polarity bit ecs0 ecs1 ecs6 figure 5. ecspld logic array general pld the general pld (gpld) is used to implement system logic such as mcu loadable counters, system mailboxes or handshaking protocols. in addition, the gpld can implement random logic and state machine functions. the gpld has output and input micro ? cells (see figure 6). the micro ? cells are configured using the psdsoft development system. like the other plds, the gpld has an and array which can generate up to 109 product terms, a maximum of nine product terms for each of the twelve micro ? cells. the input and output micro ? cells are connected to the psd813fn/fh internal data bus and can be directly accessed by the microcontroller. this enables the mcu software to load data into the output micro ? cells or read data from both the input and output micro ? cells with no overhead visible to the user. this feature allows efficient implementation of system logic and eliminates the need to connect the data bus to the and logic array as required in most standard pld macrocell architectures. pins may also be driven as outputs by the mcu directly using mcu i/o mode (see page 32). if the user drives pins with mcu i/o mode, the underlying output micro ? cell may be used for embedded nodes.
preliminary psd813fn/fh 17 i/o ports gpld output micro ? cell input micro ? cells latched address out mux i/o pin mux mux mux mux d d q q q g d qd wr wr pdb product term allocator dir reg select input product terms from other micro ? cells polarity select up to 9 product terms clock select pr di ld d/t ck cl q d/t/jk ff select pt clear pt clock global clock pt output enable ( oe ) micro ? cell feedback i/o port input ale pt input latch gate/clock mcu load pt preset mcu data in comb. reg select micro ? cell to i/o port allocator (mcell ab only) gpld output to other i/o ports pld input bus pld input bus mcu address / data / control bus micro ? cell out to mcu data write control and array gpld output figure 6. the gpld and i/o port plds (cont.)
psd813fn/fh preliminary 18 output micro ? cell eight of the output micro ? cells are connected to port c pins (except pc2) and are named as mcellc0-7. the remaining four micro ? cells can be connected to port a or port b and are named as mcellab4-7. if an mcellab output is not assigned to a specific pin in psdabel, the micro ? cell allocator will assign it to either port a or b. table 10 shows the micro ? cells and port assignment. seven of the 12 output micro ? cells are dedicated to controlling the flash memory in this multi-chip module. max data bit for native borrowed loading or output port product product reading in psd8xxf micro ? cell assignment terms terms 8-bit mode assignment mcellc0 port c0 4 5 d0 wrf mcellc1 port c1 4 5 d1 rdf mcellc2 * 45d2 ** mcellc3 port c3 4 5 d3 a14f mcellc4 port c4 4 5 d4 a16f mcellc5 port c5 4 5 d5 a17f mcellc6 port c6 4 5 d6 a18f mcellc7 port c7 4 5 d7 csf mcellab4 port a4, b4 3 6 d4 ** mcellab5 port a5, b5 3 6 d5 ** mcellab6 port a6, b6 3 6 d6 ** mcellab7 port a7, b7 3 6 d7 ** table 10. output micro ? cell port and data bit assignments the product term allocator all micro ? cells have the same cell architecture except mcellc0-mcellc7 have four native product terms and mcellab4-mcellab7 have three native product terms. the gpld also has a product term allocator with which the psdcompiler can automatically borrow product terms from one micro ? cell to another. the mcellc may borrow up to five product terms from other micro ? cells for a total of nine product terms. the mcellab has three native product terms and can borrow up to six product terms. borrowing allows micro ? cell outputs needing more product terms to use the unused product terms of others and is transparent to the user. the architecture of the 12 output micro ? cells, as shown in figure 6, consists of native product terms and borrowed product terms from other micro ? cells. the polarity of the product term input is controlled by the xor gate. the micro ? cell can implement either sequential logic, using the flip-flop element, or combinatorial functions. the multiplexor selects the combinatorial or the sequential logic as the micro ? cell output. the multiplexor output can drive a port pin and has also a feedback path to the and array inputs. micro ? cell flip-flop type the flip-flop in the micro ? cell can be configured as a d, toggle, jk or sr type by using psdabel in psdsoft. the flip-flop clock, preset and clear inputs are driven from a product term of the and array. alternatively, the device clock input (clkin) can be used for the flip-flop. the preset and clear are active high inputs; the flip-flop is clocked by the rising edge of the clock input. plds (cont.) * * internal node only. ** general purpose use.
preliminary psd813fn/fh 19 loading and reading the micro ? cells the gpld micro ? cells occupy a memory location in the mcu address space as defined by the csiop (refer to the i/o section). the flip-flops in each of the 12 micro ? cells can be loaded from the data bus by a microcontroller write bus cycle to the micro ? cell (see i/o port section for micro ? cell addresses). a ??in the data bit that associates with the micro ? cell will load a ??to the flip-flop, a ??in the data bit will load a ??to the flip-flop. the loading bus cycle takes priority over other flip-flop inputs that include the preset, clear and clock. see table 11 for the data bits that are connected to the micro ? cells. the ability to load the flip-flops and read them back is useful in such applications as loadable counters, shift registers, mailboxes or handshaking protocols. plds (cont.) ld din clk in pr clr q 1 1xxxx1 1 0xxxx0 0 x normal flip-flop function table 11. micro ? cell flip-flop loading note: ld is ??when the mcu writes to the micro ? cell address the output enable the micro ? cell can be connected to a psd813fn/fh i/o pin as pld output. the output enable of each of the port pin output driver is controlled by a single product term (.oe) from the and array ored with the direction register output. upon power up, if no output enable (.oe) equation is defined and the pin is declared as a pld output in psdsoft, the pin is enabled. if the micro ? cell output is declared as internal node and not as port pin output in the psdabel file, then the port pin can be used for other i/o functions (such as mcu i/o mode). the internal node feedback can be routed as an input to the and array. input micro ? cell the input micro ? cell as shown in figure 6 is used to latch, register or pass incoming port signals prior to driving them onto the pld input bus. the outputs of these micro ? cells can also be read by the microcontroller through the internal data bus. the gpld has 23 input micro ? cells, one for each pin of ports a, b and c (except pc2). the input micro ? cells are individually configurable. the enable/clock for the latch and flip-flop is driven by a multiplexor whose inputs are a product term from the gpld and array and the mcu address strobe (ale). each product term output is used to latch/clock four input micro ? cells. port inputs [3:0] can be controlled by one product term and [7:4] can be controlled by another one. the input micro ? cell configurations are specified by equations written in psdabel. outputs of the micro ? cells can be read by the microcontroller via the ?nput micro ? cell buffer. see the i/o port section on how to read the micro ? cells. input micro ? cells can use the ale to latch the higher address bits (a31 ?a16). the latched addresses are routed to the pld as inputs. the input micro-cell is particularly useful in handshaking communication applications where two processors wish to pass data between each other through a commonly accessible storage. figure 7 shows a typical configuration where the master mcu writes to the port a data out register that is read by the slave mcu via the activation of the ?lave-read output enable product term. the slave mcu can write to port a input micro ? cells by activating the ?lave- wr?product term. the master mcu can then read the input micro ? cells. the ?lave-read?and ?lave-wr?signals are product terms that are derived from the slave mcu inputs of rd, wr, and slave_cs.
psd813fn/fh preliminary 20 master mcu mcu-rd mcu-rd mcu-wr slave wr slave cs mcu-wr d [ 7:0 ] d [ 7:0 ] gpld dq qd port a data out register port a input micro ? cell port a slave read slave mcu rd wr psd813fn/fh figure 7. handshaking communication using input micro ? cells plds (cont.)
preliminary psd813fn/fh 21 bus interface mcu data bus cntl0 cntl1 cntl2 pd0** adio0 8031 8 wr rd psen ale a0 68330 8 r/w ds * ale a0 80198 8 wr rd * ale a0 68hc11 8 r/w e * as a0 80c251 *** 8 wr rd psen ale a0 z8 8 r/w ds ** a0 neuron 3150 8 r/w ds ** a0 table 12. microcontroller busses and control signals the ?o-glue logic?psd813fn/fh microcontroller bus interface can be directly connected to the most popular microcontrollers and their control signals. some of these microcontrollers with their bus types and control signals are shown in table 12. the interface type is specified using the psdsoft tools. ** *not used cntl2 pin can be configured as gpld input. other not used pins (cntl2, pd0) can be configured *** for other i/o functions. * **ale/as input is optional for microcontrollers with a non-multiplexed bus. ***8051 compatible mode only. table 12 shows the names of the psd813fn/fh bus interface control pins and their functions. the control pins have multiple functions and can be configured to interface to many microcontrollers. depending on the microcontroller, some of the control input pins are not required and may be used as gpld input or other i/o functions. specific examples of interfaces to different microcontrollers are provided in the following sections. for microcontrollers that have more than 16 address lines, port a and b pins may be used as additional address inputs
PSD813FH interface to a multiplexed bus figure 8 shows an example of a system using a microcontroller with a multiplexed bus and a PSD813FH. the adio port on the PSD813FH is connected directly to the microcontroller address/data bus. the bus may be multiplexed only on one byte (eight-bit data) or on both bytes (sixteen-bit data). the ale latches the address lines internally; latched addresses can be brought out to port a or b. the PSD813FH drives the adio data bus only when one of its internal resources is accessed and the rd input is active. psd813fn/fh preliminary 22 bus interface (cont.) micro - controller wr rd bhe ale reset ad [ 7:0 ] a [ 15:8 ] a [ 15: 8 ] a [ 7: 0 ] adio port port a port b port c wr ( cntrl0 ) rd ( cntrl1 ) bhe ( cntrl2 ) rst ale ( pd0 ) port d ( optional ) ( optional ) PSD813FH figure 8. an example of a typical 8-bit multiplexed bus interface
preliminary psd813fn/fh 23 bus interface (cont.) micro - controller wr rd bhe ale reset d [ 7:0 ] a [ 15:0 ] a [ 23:16 ] d [ 7:0 ] adio port port a port b port c wr ( cntrl0 ) rd ( cntrl1 ) bhe ( cntrl2 ) rst ale ( pd0 ) port d (optional) psd813fn figure 9. an example of a typical non-multiplexed bus interface, 8-bit data bus psd813fn interface to a non-multiplexed bus figure 9 shows an example of a system using a microcontroller with a non-multiplexed bus and a psd813fn. the address bus is connected to the adio port, and the data bus is connected to port a (d[7:0]). the data ports are in tri-state mode when the psd813fn is not accessed by the microcontroller. should the system address bus exceed sixteen bits, port b may be used as additional address inputs.
psd813fn/fh preliminary 24 microcontroller interface examples figures 10 and 11 show examples of the basic connections between the psd813fn/fh and some popular microcontrollers. the psd813fn/fh control input pins are labeled as the microcontroller function for which they are configured. the mcu interface is specified using the psdsoft tools. the pc2 pin should be grounded if vstby is not used. 80c31 figure 10 shows the interface to the 80c31 which has an 8-bit multiplexed address/data bus. the lower address byte is multiplexed with the data bus. the microcontroller rd and wr signals may be used for accessing internal sram and i/o ports while the psen signal is used to read the eprom. the ale input (port d pd0) latches the address. refer to the memory section for additional 80c31 operating modes. 68hc11 figure 11 shows an interface to an 68hc11 where the PSD813FH is configured in 8-bit multiplexed mode with e and r/w settings. the ecspld can generate the read and wr signals for external on board devices. the cntl2 pin is not used and can be used as a pld input. 80c251 the intel 80c251 microcontroller features a user-configurable bus interface with two possible bus configurations as shown in table 13. bus interface (cont.) configuration 80c251 connecting to page mode read/write psd813fn/fh pins pins wr cntl0 non-page mode, 80c31 compatible 1 rd cntl1 a [ 7:0 ] multiplex with d [ 7:0 } psen cntl2 2 wr cntl0 non-page mode psen only cntl1 a [ 7:0 ] multiplex with d [ 7:0 } table 13. 80c251 configurations configuration 1 is 80c31 compatible. the bus interface to the PSD813FH is identical to that shown in figure 10. there is only one read input (psen) connected to the cntl1 pin on the PSD813FH. the a16 connection to the pa0 pin allows for a larger address input to the PSD813FH.
preliminary psd813fn/fh 25 ea/vp x1 x2 reset reset int0 int1 t0 t1 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 ( vstby ) pc2 pc1 pc3 pc4 pc5 pc6 pc7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 adio0 adio1 adio2 adio3 adio4 adio5 adio6 adio7 adio8 adio9 adio10 adio11 adio12 adio13 adio14 adio15 cntl0 (wr) cntl1(rd) cntl2 (psen) pd0-ale pd1 pd2 rstin rd wr psen ale/p txd rxd reset 29 28 27 25 24 23 22 21 30 39 31 19 18 9 12 13 14 15 1 2 3 4 5 6 7 8 38 37 36 35 34 33 32 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 31 32 33 34 35 36 37 39 40 41 42 43 44 45 46 47 48 50 49 10 9 8 7 6 5 4 3 2 52 51 PSD813FH 80c31 ad [ 7:0 ] ad [ 7:0 ] 21 22 23 24 25 26 27 28 17 16 29 30 a8 a9 a10 a11 a12 a13 a14 a15 rd wr psen ale 11 10 reset 20 19 18 17 14 13 12 11 * ** ** figure 10. interfacing the PSD813FH with an 80c31 mcu bus interface (cont.) * * if not used, pc2 must be grounded. ** reserved for internal flash memory control.
psd813fn/fh preliminary 26 bus interface (cont.) 9 10 11 12 13 14 15 16 adio0 adio1 adio2 adio3 ad104 ad105 adio6 adio7 adio8 adio9 adio10 adio11 ad1012 ad1013 adio14 adio15 cntl0 (r / w) cntl1(e) cntl 2 pd0?s pd1 pd2 rstin 20 21 22 23 24 25 3 5 4 6 42 41 40 39 38 37 36 35 ad0 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a8 a9 a10 a14 a15 a13 a11 a12 ad1 ad2 ad3 ad4 ad5 ad6 ad7 e as r/w xt ex reset irq xirq pa0 pa1 pa2 pe0 pe1 pe2 pe3 pe4 pe5 pe6 pe7 vrh vrl pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pc0 pc1 pc3 pc4 pc5 pc6 pc7 pd0 pd1 pd2 pd3 pd4 pd5 moda e as r/w 31 30 31 32 33 34 35 36 37 39 40 41 42 43 44 45 46 48 8 9 10 49 50 47 +5v 8 7 17 19 18 34 33 32 43 44 45 46 47 48 49 50 52 51 30 29 28 27 29 28 27 25 24 23 22 21 20 19 18 17 14 13 12 11 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 7 6 5 4 3 2 52 51 modb 2 68hc11 PSD813FH reset reset ad[7:0] ad[7:0] ( vstby ) pc2 * ** ** figure 11. interfacing the PSD813FH with a 68hc11 * * if not used, pc2 must be grounded. ** reserved for internal flash memory control.
preliminary psd813fn/fh 27 i/o ports there are four programmable i/o ports: ports a, b are 8 bits, port c is seven bits and port d is three bits. the ports can be configured to function in different modes of operation. each port pin is individually configurable allowing a single port to perform multiple functions. the configuration is defined either using the psdsoft tools or by the microcontroller writing to on-chip registers. general port architecture the general architecture of the i/o port is shown in figure 12. individual port diagrams are shown in figures 14, 15 and 16, and will be discussed in the section below. if the psd813fn/fh is configured to a non-multiplexed bus mode, port a and/or port b are connected to the mcu data bus and are not available as general purpose i/o ports. as shown in figure 12, the port pins contain an output multiplexer whose selects are driven by the configuration defined in psdabel and the control registers. inputs to the multiplexer include the following: o output data from the data out register in the mcu i/o output mode o latched address outputs o gpld micro ? cell output or ecspld external chip select output o ecspld external chip select output the above inputs are also connected to the port data buffer (pdb) for feedback to the internal data bus that can be read by the microcontroller. the pdb is a three-state buffer operating like a multiplexer that allows only one source to be read at a time. the pdb also has inputs from the direction register, control register and direct port pin input (data in ). the port pins tri-state output driver enable is controlled by a two input or gate whose inputs come from the gpld and array enable product term (.oe) and the direction register. if the enable product term of the array output is not defined, then the direction register has sole control of the buffer. refer to tables 14 and 15 on how the direction of a port pin is configured. direction register bit port pin mode 0 input 1 output table 14. port pin direction control, output enable p.t. not defined direction register bit output enable p.t.* port pin mode 0 0 input 0 1 output 1 0 output 1 1 output table 15. port pin direction control, output enable p.t. defined * port d does not have an output enable p.t. the register contents can be altered by the microcontroller. the pdb feedback path allows the microcontroller to check the contents of the registers. the a, b and c ports have embedded input micro ? cells which can be configured as a latch, a register or direct input to the gpld. the latch and register are clocked by the address strobe or a product term from the gpld and array. the output from the input micro ? cell drives the pld input bus and can be read by the microcontroller. refer to the input micro ? cell description in the pld section. port a has additional logic (not shown in figure 12) that enables it to operate in peripheral i/o mode when the pio bit in the vm register is set.
psd813fn/fh preliminary 28 internal data bus data out reg. dq d g q dq dq wr wr wr muxed address/data micro ? cell outputs enable product term ( .oe ) ext.cs ale read mux p d b gpld - input control reg. dir reg. input micro ? cell enable out data in output select output mux port pin data out latched address figure 14. general i/o port architecture i/o ports (cont.)
preliminary psd813fn/fh 29 port operating modes the i/o ports have several modes of operation as shown in table 16. some modes may be selected using the psdabel tool and programmed into the device using non-volatile memory (nvm) that is active when power is applied and cannot be altered unless the device is reprogrammed. if a mode is not defined in psdsoft, then other modes can be set by the microcontroller writing to the port configuration registers at run-time. the pld i/o, data port and address input modes are nvm configurations. the other modes are initiated by the microcontroller. if the nvm modes are not selected, the port can be altered dynamically between mcu i/o or address out modes by writing to the control register. each bit of the eight-bit control register may store a ?? setting its respective bit in the port to mcu i/o, or to a ?? setting it to address out. the direction register or the output enable product term determine if the pin is input or output. table 16 summarizes the operating modes of the i/o ports. not all the functions are available to every port. table 17 shows how and where the different modes are configured. port mode port a port b port c port d configured at run-time mcu i/o yes yes yes yes pld i/o mcellab outputs pa7 4 pb7 4 no mcellc outputs no no no no ecspld outputs pa3 0 pb3 0 pd2 0 zpld inputs yes yes reserved yes address out yes yes (a7 0, for (a7 0) a15 8) flash no yes address in yes yes memory no no data port yes control (d7 0) plus no no open drain yes yes vstby no yes (pa7 4) (pb7 4) slew rate yes yes yes yes (pa3 0) (pb3 0) peripheral i/o yes no no yes table 16. port operating modes i/o ports (cont.)
psd813fn/fh preliminary 30 i/o ports (cont.) control direction vm defined in defined in register register register mode psdabel psdconfiguration setting setting setting mcu i/o declare pins only na 0 1 = output, na 0 = input (note 1) pld i/o logic equations na na* (note 1) na data port na specify bus type na na na (port a,b) address out declare pins only na 1 1 (note 1) na (port a,b) address in logic equation for na na na na (port a,b,c) input micro ? cells peripheral i/o logic equations na na na pio bit = 1 (port a) (psel0 & 1) table 17. port operating mode settings * na ?not applicable note 1: the direction of the port a, b, c pins are controlled by the direction register ored with the individual output enable product term (.oe) from the gpld and array. pld i/o mode the pld i/o mode uses the port as an input to the gpld input micro ? cell, and/or as an output from the gpld, ecspld. the port assignments are shown in tables 9 and 10. the output can be tri-stated with a control signal defined by a product term (.oe) from the pld, or, by setting a zero in the direction register. the direction register must not be set to ??if the pin is defined as a pld input pin. the pld i/o mode is specified in psdabel by declaring the port pins, then writing an equation assigning it to the port. mcu i/o mode in the mcu i/o mode the microcontroller uses the psd813fn/fh ports to expand its own i/o ports. the ports on the psd813fn/fh are mapped into the microcontroller address space. the addresses of the ports are listed in table 22. a port pin will be put into mcu i/o mode by writing a zero to the corresponding bit in the control register. the direction may be changed by writing to the direction register for the port where a ??makes it an output and a ??an input. the output enable product term also can change the direction of the pin (see table 14 and 15). when the pin is configured as output, the content of the data out register drives the pins. in input mode, the microcontroller reads the port input through the data in buffer ports c and d do not have a control register and are in mcu i/o mode by default for pins that are not configured as pld i/o. address out mode for microcontrollers with a multiplexed address/data bus, the ports in address out mode drive latched addresses to external devices. address [7:0] are always assigned to port a. see table 23 for the address output pin assignments on ports a and b. the direction register and the control register must be set to a ??for port pins using address out mode. in non-multiplexed 8 bit bus mode, address[7:0] are available on port b in address out mode. port operating modes (cont.)
preliminary psd813fn/fh 31 i/o ports (cont.) port operating modes (cont.) address in mode for microcontrollers that have more than 16 address lines, the higher addresses can be connected to port a, b, or c. the address input can be latched in the input micro ? cell by ale. any input that is included in the dpld equations for the psd flash, otp boot, or eprom is considered as address input. data port mode port a can be used as a data bus port for a microcontroller with a non-multiplexed address/data bus. the data port is connected to the data bus of the microcontroller. the general i/o functions are disabled in port a if the port is configured as data port. see figure 9. peripheral i/o mode only port a supports the peripheral i/o mode whereby all of port a serves as a tri-stateable bi-directional data buffer of the microcontrollers data bus. peripheral mode is enabled by setting bit 7 of the vm register to a ?? figure 13 shows that when peripheral mode is enabled and either psel0 and psel1 from the dpld is active, port a acts as a bi-directional buffer for the microcontroller d[7:0] data bus. the buffer is tri-stated when psel 0 or 1 is not active. the peripheral i/o mode can be used to interface with external peripherals. use psdabel to write equations that contain the keyboards psel0 and psel1. open drain/slew rate mode ports a (pins pa7-4) and b (pins pb7-4) and c (except pc2) can be configured as open drain instead of cmos outputs. the open drain configuration is useful for sinking large currents to operate leds, for example. the open drain mode is enabled by writing a ??to the corresponding bit in the drive register. port a (pa30), port b (pb30) and port d can be configured as ecspld outputs that have a high slew rate. the high slew rate is enabled by writing a ??to the corresponding bit in the drive register. rd psel0 psel1 vm register bit 7 wr pa0 - pa7 d0-d7 data bus figure 13. port a peripheral mode
psd813fn/fh preliminary 32 i/o ports (cont.) port registers each port has a set of registers used for configuration (pcr, port configuration registers) and data transfers (pdr, port data registers). the contents of the registers can be accessed by the microcontroller through normal read/write bus cycles at the addresses given in table 22. the address of the registers is comprised by that of the csiop output from the dpld plus an address offset as listed in the tables. the pins of a port are individually configurable and each bit in the register controls its respective pin. for example, bit 0 in a register refers to bit 0 in its port. the three port configuration registers, shown in table 18, are used for setting the port configuration. each register is set to zero at power up. register name port mcu access control a,b write/read direction a,b,c,d write/read drive* a,b,c,d write/read table 18. port configuration registers * note: see table 20 for drive register bit definition. control register a ??in the control register sets the port pin to mcu i/o for port a and b. a ??sets the port pin to address out mode. the default mode is mcu i/o. direction register controls the direction of data flow in the i/o ports. a ??configures the port to be an output, and a ??to an input. the i/o configuration can be read from the direction register. the default mode is input. as shown in figure 12, the direction of data flow in port a,b and c pins are also controlled by the output enable (.oe) product term from the gpld and array. if the .oe product term is not active, the direction register has sole control of the pin direction. an example of a configuration for a port with the three least significant bits set to output and the remainder set to input is shown in table 19. the port d register has only the three least significant bits active. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0000 111 table 19. port direction assignment example
preliminary psd813fn/fh 33 i/o ports (cont.) port registers (cont.) drive register the drive register configures the pin driver as open drain, or in the case of ecspld outputs, sets the pin to operate in high slew rate. an external pull-up resistor is not required when the pin is in the slew rate mode. for ports a and b the register sets different functions for the lower and higher nibbles. the four upper bits set the corresponding bits the as cmos (?) or open drain (?) driver. the four lower bits are used for slew rate control. the slew rate is a measurement of the rise and fall times of the output. a higher slew rate means a faster output response while a lower slew rate is a slower, lower slope, response. the pin operates in high slew rate when the corresponding bit in the drive register is set to ?? table 20 shows the drive registers of port a, b, c and d and which pin has the open drain or slew rate configuration. drive bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register port a open open open open slew slew slew slew drain drain drain drain rate rate rate rate port b open open open open slew slew slew slew drain drain drain drain rate rate rate rate port c * open open open open open na open open drain drain drain drain drain drain drain port d na na na na na slew slew slew rate rate rate table 20. drive register pin assignment note: na = not applicable, bit should set to ?? * port c pins are dedicated to flash memory control in this multi-chip module product.
psd813fn/fh preliminary 34 i/o ports (cont.) port data registers the port data registers, shown in table 21, are used by the microcontroller to write or read data to or from the ports. table 21 shows the register name, the ports having each register type and microcontroller access for each register. the registers are described below. register name port mcu access data in a,b,c,d read ?the input on pin data out a,b,c,d write/read feedback output micro ? cell a,b,c read ?outputs of micro ? cells write ?loading micro ? cells flip-flop input micro ? cell a,b,c read ?outputs of the input micro ? cells enable out a,b,c read ?the output enable control of the port driver table 21. port data registers data in port pins are connected directly to the data in buffer. in mcu i/o input mode, the pin input is read through the data in buffer. the mcu can always read the state of a port pin using this method, regardless of what is driving the pin. data out register stores output data written by the mcu in the mcu i/o output mode. the contents of the register are driven out to the pins if the direction register or the .oe product term is set to ?? the contents of the register can also be read back by the microcontroller. output micro ? cell the gpld output micro ? cells occupy a location in the microcontrollers address space. the microcontroller can read the output of the micro ? cells. writing to the micro ? cell loads data to the micro ? cell flip-flops. refer to the pld section for more detail. input micro ? cell the input micro ? cells can be used to latch or store external inputs. the outputs of the input micro ? cells are routed to the pld input bus and also can be read by the microcontroller. refer to the pld section for detail description. enable out the enable out buffer allows the microcontroller to read the outputs of the ?r?gate that is the enable input to the port output driver. a ??indicates the driver is in output mode, a ? indicates the driver is in tri-state and the pin is in input mode.
preliminary psd813fn/fh 35 i/o ports (cont.) port data registers (cont.) register i/o address offset the base address of the registers is defined in the csiop equation that occupies 256 bytes of address space and is defined by the user in psdsoft. the lower address byte a[7:0], or address offset, selects the register. table 22 shows the address offset for all mcus except those motorola microcontrollers with a 16-bit data bus. for example, when the csiop is defined to occupy the address range of 1000h to 10ffh in psdabel, the address of the port a control register is then 1002h. register name port a port b port c port d data in 00 01 10 11 control 02 03 data out 04 05 12 13 direction 06 07 14 15 drive 08 09 16 17 input micro ? cell 0a 0b 18 enable out 0c 0d 1a output micro ? cell 20 20 21 table 22. i/o register address offset (relative to csiop) microcontroller port a (3:0) port a (7:4) port b (3:0) port b (7:4) 8-bit multiplexed bus address (3:0) address (7:4) address (3:0) address (7:4) (PSD813FH) 8-bit non-multiplexed bus n/a n/a address (3:0) address (7:4) (psd813fn) table 23. i/o port latched address output assignments port a and b ? functionality and structure port a and b have similar functionality and structure as shown in figure 14. the two ports can be configured to perform one or more of the following functions: o mcu i/o mode o gpld output micro ? cells mcellab[7:4] can be connected to port a pa[7:4} or port b pb[7:4]. o ecspld output external chip select output can be connected to either port a pa[3:0] or port pb[3:0]. o latched address output ? provide latched address output per table 23. o address in ? additional high address inputs using the input micro ? cells. o open drain/slew rate pins pa[3:0] and pb[3:0] can be configured to open drain mode pins pa[7:4] and pb[7:4] can be configured to fast slew rate o data port port a to d[7:0} for 8 bit non-multiplexed bus o peripheral mode ? port a only n/a = not applicable.
psd813fn/fh preliminary 36 i/o ports (cont.) internal data bus data out reg. dq d g q dq dq wr wr wr address mcell ab [ 7:4 ] enable product term ( .oe ) ecs [ 3:0 ] ale read mux p d b gpld - input control reg. dir reg. input micro ? cell enable out data in output select output mux port a or b pin data out address a [ 7:0 ] or a [ 15:8 ] figure 14. port a and b structure
preliminary psd813fn/fh 37 i/o ports (cont.) port c ? functionality and structure all port c pins are configured as pld i/o mode for flash memory controls (except pc2). the other port c i/o functions are disabled (multi-chip module only). pc0 wrf flash memory write signal pc1 rdf flash memory read signal pc2 vstby sram vstby pc3 a14f flash address a14 pc4 a16f flash address a16 pc5 a17f flash address a17 pc6 a18f flash address a18 pc7 csf flash chip select port c pin pc2 is dedicated as the vstby pin for sram battery backup and can not be used for other functions. port d ? functionality and structure port d has only three i/o pins, does not support address out mode, and no control register is required. port d can be configured to perform one or more of the following functions: o mcu i/o mode o ecspld output ? external chip select output o pld input ? direct input to pld, no input micro ? cells o slew rate ? pins can be set up for fast slew rate port d pins can be configured in psdsoft as input pins for other dedicated functions: o pd0 ? ale, as address strobe input o pd1 ? clkin, as clock input to the micro ? cells flip-flops and apd counter o pd2 ? csi, as active low chip select input. a high input will disable the psd eprom/sram.
psd813fn/fh preliminary 38 i/o ports (cont.) internal data bus data out reg. dq dq wr wr mcell c [ 7:0 ] enable product term ( .oe ) read mux p d b gpld - input dir reg. input micro ? cell enable out data in output select output mux port c pin data out (all port c pins are dedicated to flash memory control for multi-chip module) figure 15. port c structure
preliminary psd813fn/fh 39 i/o ports (cont.) internal data bus data out reg. dq dq wr wr ecs [ 6:4 ] read mux p d b gpld - input dir reg. data in output select output mux port d pin data out figure 16. port d structure
psd813fn/fh preliminary 40 memory block the psd813fn/fh are a multi-chip module that includes a psd6xx die and a 4 megabit flash memory die configured to operate as a 1 mb device. the psd813fn/fh includes 32 kbytes of otp boot eprom; the flash die provides 128 kbytes of flash memory. the otp boot eprom is used for system boot up and for storing the flash memory programming algorithm. the flash erase and programming algorithms are compatible to the amd and sgs-thomson embedded erase and programming algorithm tm . the flash memory can be erased or programmed while the microcontroller is executing code from the boot eprom. chip selects for the memory blocks come from the dpld and gpld decoding logic and are defined by the user in the psdsoft software. figure 17 shows the organization of the memory block. boot eprom the chip selects (csboot0?) for the otp boot eprom are generated from the dpld address decoder. the csboot0? are defined in 8 kbyte boundaries and should not overlap the flash memory address space. flash memory the flash die that is used on this mcm is a 4 mbit flash device but only 1 mbit will be addressed. address lines a14 and a15 are inactive during flash reads. this leaves address lines a16, a17, and a18 to page through eight 16 kbyte sectors of flash memory. each 16 kbyte sector of flash is addressed by the address lines a0a13. this flash paging is simplified by the configuration of the dpld and the gpld. fs07 are the chip selects for each block that is defined in the dpld at 16 kbyte boundaries. the designer may custom configure flash addressing schemes by the hdl equations developed in psdsoft. the use of the internal psd page register is very effective in this application. see figure 17 and table 24. note: unlike flash reads, whenever the embedded flash algorithms are exercised (write, erase, id, etc), address line a14 to the flash is enabled (as configured by the hdl) to pass commands from the mcu to the flash die. address line a15 to the flash die is permanently grounded. seven of the pins and micro ? cells on the psd6xx die are reserved for generation of flash memory control signals. the address lines a14f, a16f, a17f, a18f, and the chip select csf are generated based on the fs0? inputs to the gpld. refer to appendix a for the operation and programming algorithm for the flash memory. sram the sram has 4 kbits of memory, organized as 512 x 8. the sram is enabled by the chip select signal rs0 from the dpld. the sram has a battery back-up (stby) mode. this back-up mode is automatically invoked when the v cc voltage drops under the vstdby voltage. the vstdby voltage is connected only to the sram and cannot be lower than 2.0 volts. memory select map the boot eprom, flash memory, and sram chip select equations are defined in the abel file in terms of address and other dpld inputs. the memory space for the flash chip select (fs0?) should not be larger than the 16k flash block it is selecting. the boot eprom block should not be larger than 8 kbytes. the following rules govern how the psd813f memory selects/space are defined: o the flash blocks address space cannot overlap among blocks. o the flash blocks address space cannot overlap the boot eprom, the sram and i/o address space. o sram and internal i/o address space cannot overlap. o sram and internal i/o space can overlap boot eprom space, with priority given to sram or i/o. the portion of boot eprom which is overlapped cannot be accessed.
preliminary psd813fn/fh 41 memory block (cont.) figure 17. psd813fn/fh memory block address bus a [ 15:0 ] a [ 14:0 ] a [ 13:0 ] d [ 7:0 ] d [ 7:0 ] d [ 7:0 ] a [ 15:0 ] fs [ 7:0 ] fs [ 7:0 ] pgr [ 3:0 ] pgr [ 3:0 ] rd wr psen reset dpld gpld csboot csiop rs0 pc3 pc4 pc1 pc0 pc7 a14f a15f a16f pc5 a17f pc6 a18f rdf wrf csf flash memory sram 0.5 kb otp boot eprom 128 kb data bus 32 kb signal pin/macrocell function example equations name based on the 8031 bus wrf pin pc0 write input wrf = wr; rdf pin pc1 read input rdf = ! (!rd # !psen); a14f pin pc3 flash memory a14f = a14 & pgr3 a14 input a16f pin pc4 flash memory a16 input a16f = fcs1 # fcs3 # fcs5 # fcs7; a17f pin pc5 flash memory a17 input a17f = fcs2 # fcs3 # fcs6 # fcs7; a18f pin pc6 flash memory a18 input a18f = fcs4 # fcs5 # fcs6 # fcs7; csf pin pc7 flash memory !csf = fcs0 # fcs1 # fcs2 # fcs3 # select fcs4 # fcs5 # fcs6 # fcs7; table 24. flash memory control signals
psd813fn/fh preliminary 42 vm reg bit 1 vm reg bit 0 run-time mode rd_en psen_en 0 0 separate space mode (default at reset) 0 1 combined program space mode 1 0 combined data space mode 1 1 combined space mode table 25. vm register note: bits 6-2 are not used. use of bit 7 is described in the peripheral i/o mode section. memory select for 8031 microcontrollers the 8031 family of microcontrollers have a separate address space for program memory (enabled by psen) and data memory (enabled by rd). normally, the boot eprom would lie in program address space and the sram would lie in data address space. the psd813fn/fh allows the boot eprom and sram address space to reside in program space, data space or both. this flexibility enables several system designs. for example, if the user desires to execute a program that resides in sram, the sram would have to occupy program address space (enabled by psen). likewise, the user may devote a block of boot eprom to contain data lookup tables, requiring the boot eprom to occupy data address space (enabled by rd). the internal psd boot eprom and sram each have their own output enable. combinations of psen and rd drive these output enables and are determined by bits set at run-time by the mcu in the vm register (see table 25). the schematic representation can be seen in figure 19 and the action of bit 0 and bit 1 of the vm register is shown. there are four modes of operation that can be selected by the mcu at run-time as shown in table 25. all of these modes assume there are no overlapping address assignments for blocks of boot eprom and sram. these blocks of memory may reside in the same 64k program or data space, but not share any physical addresses within the 64k. example 1: boot eprom block 0 and sram cannot both start at address 0000. example 2: boot eprom block 2 in program space and boot eprom block 3 in data space cannot both start at address 8000). o separate space mode program memory space is separate from data memory space. this default state ties the boot eprom output enable to psen only, and ties the sram output enable to rd only. o combined program space mode this mode allows the sram to reside in program space (to be enabled by psen as well as rd). o combined data space mode this mode allows the boot eprom to reside in data space (to be enabled by rd as well as psen). o combined space mode this mode allows both the boot eprom and sram to reside in either program space or data space (either memory may be accessed by psen or rd). memory blocks (cont.)
preliminary psd813fn/fh 43 memory blocks (cont.) memory select for 8031 microcontrollers (cont.) mixed mode is another mode of operation that is not set by the mcu at run-time but is set by an nvm bit from the psd device programming file that psdsoft creates. this mode deals with overlapping boot eprom addresses such as when two psd boot eprom blocks start at address 8000, but one is in program space and the other is in data space. o mixed mode this mode allows individual boot eprom blocks with overlapping addresses to be configured in either program space or data space. the csbootx chip select equations for the overlapping blocks must be qualified with the 8031 rd input. an active low rd will select boot eprom blocks in data space and disable the blocks in program space. the nvm bit is automatically set by psdsoft if the keyword rd is used in any csbootx equation. this nvm bit is equivalent to setting bit 1 in the vm register, only it is there from system power-up. here are some example csbootx equations: csboot0 = address >= ^h8000 & address <= ^h1fff & rd; ?esides program space csboot1 = address >= ^h8000 & address <= ^h1fff & !rd; ?esides data space there are two reasons to use this mode. first, this mode must be used if psd boot eprom addresses overlap each other but reside in different spaces. second, this mode can be used if psd boot eprom block addresses do not overlap but it is desired to have one or more boot eprom blocks reside in data space and the designer wants this to be set in nvm configuration from power up (not set at run-time). important: for boot eprom blocks that reside in data space, the access time is calculated from rd valid to data valid. the designer must ensure that eprom access time is sufficient for the system, or else use the vm register bit 1 without overlapping addresses.
psd813fn/fh preliminary 44 memory blocks (cont.) dpld csboo t0? rs0 psen rd boot eprom sram cs cs oe oe figure 18. 8031 memory modes ? separate space mode dpld csboo t0? rs0 psen boot eprom sram oe oe rd rd vm reg bit 1 vm reg bit 0 figure 19. 80c31 memory mode ? combined space mode
preliminary psd813fn/fh 45 the psd813fn/fh offers a number of configurable power savings options. the designer may choose a wide array of options that range from excellent power savings with no performance loss to maximum power savings at the expense of a slight performance loss. these power saving functions are designed to occur automatically in the background and most can be set up by the mcu at run-time. note that these features only apply to the psd6xx portion of this multi-chip module. the monolithic psd8xxf members will apply these power reduction features to the nvm sections as well. the automatic power down (apd) mode apd logic puts the psd813fn/fh into power savings mode by monitoring the activity of the address strobe (ale/as). the apd unit is a down-counter that is reset by the active state of ale/as. see figure 20. this apd counter is clocked by an external free running clock signal that is routed in on the clkin pin (port d-pd1). the apd counter will reach terminal count after 15 transitions of clkin. if ale/as is not active for 15 cycles of clkin, the apd counter will reach terminal count and force power down mode if enabled. the psd will come out of power down mode immediately after the first active pulse of ale/as with no performance penalty. during power down mode, the psd boot eprom, sram, and mcu bus interface is disabled. the gpld and ecspld sections operate as normal during power down mode. table 26 shows the effects of power down mode on psd i/o. power management unit port function pin level mcu i/o no change pld out no change address out undefined data port hi-z tri-state peripheral i/o hi-z tri-state table 26. power down effect on ports apd functions are enabled by the mcu at run-time using the power management mode registers pmmr0 and pmmr1 as shown in table 28. figure 21 shows a typical flow for mode setup. power down mode may also be achieved by deasserting the csi input as described later. sleep mode sleep mode is an extension of power down mode which provides maximum power savings at the expense of a small performance loss. if sleep mode is enabled, sleep mode will occur when power down mode occurs and exit when power down mode exits. in sleep mode, the gpld and ecspld still monitor inputs and respond to them, however, the gpld and ecspld propagation delays are extended to t pd4 . when sleep mode is exited, the gpld and ecspld will continue to have the extended delay of t pd4 for a ?ake-up?period of t pd5 . also, the first access of boot eprom or sram that occurs while coming out of sleep mode will incur an extended access time of t lvdv1 . after that, psd eprom and sram access times will be normal. sleep mode is enabled by the mcu at run-time using the power management mode register pmmr1 as shown in table 28. figure 21 also shows a typical flow for mode setup.
psd813fn/fh preliminary 46 power management unit (cont.) pld access pld recovery time recovery time propagation to normal access to normal mode delay operation time access power down normal tpd 0 no access tlvdv (note 1) sleep t pd4 t pd5 no access tlvdv1 (note 2) (note 3) table 27. summary of psd813fn/fh timing and standby current during power down and sleep mode notes: 1. power down does not affect the operation of the pld. 2. in sleep mode any input to the pld will have a propagation delay of t pd4 . 3. pld recovery time to normal operation after existing sleep mode. an input to the pld during the transition will have a propagation delay of t pd5 . cmiser bit the cmiser function reduces dc power consumption of the boot eprom and sram and is independent of apd logic. when cmiser is enabled, the lowest level of dc power is consumed, however, boot eprom and sram access times will be extended an additional 10 ns. see the psd dc characteristics and mcu read timing specifications in this document for more details. the csi input pin pd2 of port d can be configured in psdsoft as the psd chip select input csi. if configured as such, the csi pin will invoke power down mode (as described above) when its level is a logical one. when csi is logic zero, the psd functions normally. the csi function is independent of any run-time power saving options. if power down mode is activated from csi, exit from this mode is identical to power down mode activated by the apd logic. input clock if the psd is configured to use the clkin pin (port d pd1) for use in the pld and array and output microcells, this clock signal may be disabled during power down mode to further reduce power consumption. this feature is enabled by the mcu and run-time using the pmmr0 register as shown in table 28. note that even when the clock signal clkin is blocked by this feature, the clock signal is still active at the apd down-counter. sram standby mode the psd sram has a dedicated vstby pin (port c pc2) that can be connected to an external battery. when system v cc falls below the battery voltage at the vstby pin, the psd will automatically connect vstby as the power source for the psd sram. the sram standby current (i stby ) is typically 0.5 ? and the minimum data retention voltage is 2.0 volts. note: pin pc2 should be grounded if not used as vstby.
preliminary psd813fn/fh 47 power management unit (cont.) apd en pmmr0 bit 1 ale polarity pmmr0 bit 0 ale csi clkin apd clear logic edge detect apd counter power down ( pd ) disable bus interface eprom select sram select i/o select pd clr pd sleep mode sleep-en pmmr1 bit 1 disable eprom/sram zpld figure 20. apd logic block apd disabled set ale polarity in pmmr0 bit 0 need sleep mode enable apd set pmmr0 bit 1 = 1 disable pld clock set pmmr0 bit 4, 5 = 1 disable pld clock set pmmr0 bit 4, 5 = 1 psd813fn/fh in power down mode reset enable sleep mode set pmmr1 bit 1 enable apd set pmmr0 bit 1 = 1 psd813fn/fh in sleep mode ale idle and 15 clkin clock ale idle and 15 clkin clock yes no figure 21. enable power down flow chart
psd813fn/fh preliminary 48 bit 0 0 = ale power down polarity low 1 = ale power down polarity high bit 1 0 = automatic power down (apd) is disabled 1 = automatic power down (apd) is enabled bit 2 0 = eprom/sram cmiser is off 1 = eprom/sram cmiser is on bit 4 0 = clkin input to the pld and array is connected 1 = clkin input to pld and array is disconnected bit 5 0 = clkin input to the pld micro ? cells is connected 1 = clkin input to pld micro ? cells is disconnected bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ** pld pld * cmiser apd ale pd mcell clk array clk enable polarity 1 = off 1 = off 1 = on 1 = on 1 = high table 28. power management mode registers (pmmr0, pmmr1)** pmmr0 * * bits 3, 6 and 7 are not used, and should set to 0. ** both the pmmr0 and pmmr1 register bits are clear to zero following power up. subsequent reset pulses will not clear the registers. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 * ***** sleep * mode enable 1 = on pmmr1 bit 1 0 = sleep mode is disabled 1 = sleep mode is enabled * unused bits should be set to 0. apd ale enable bit pd polarity ale level apd counter 0 x x not counting 1 x pulsing not counting 1 1 1 counting (generates pdn after 15 clocks) 1 0 0 counting (generates pdn after 15 clocks) table 29. apd counter operation power management unit (cont.)
preliminary psd813fn/fh 49 other features page register the four-bit page register increases the addressing capability of the microcontroller by a factor of 16. the contents of the register can also be read by the microcontroller. the outputs of the page register (pgr0-pgr3) are inputs to the pld and can be included in the flash, boot eprom, or sram chip select equations. figure 24 shows the page register. the four flip-flops in the register are connected to the internal data bus d0 d3. the microcontroller can write to or read from the page register. the register can operate as an independent register and used in general purpose logic if page expansion is not needed. reset d0 -d3 r/w d0 q0 q1 q2 q3 d1 d2 d3 page reg. pgr0 pgr1 pgr2 pgr3 dpld gpld ecspld rs0, csboot0 -7, fs0 -7 pld figure 22. page register reset input the psd813fn/fh has an active low reset input which loads internal configurations and clear some of the registers. figure 33 shows the reset timing requirement. the active low range has a minimum t nlnh duration. after the rising edge of reset, the psd813fn/fh remains in the reset state during t opr range. the device must be reset at power-up prior to use. important: the psd must be out of the reset condition prior to or concurrent with the mcu coming out of reset. while the reset input is active, the pld is active and the outputs are determined by the psdabel equations. the chip status during reset and power down is shown in table 30.
psd813fn/fh preliminary 50 port configuration reset power down mode mcu i/o input unchanged pld output active depends on inputs to the pld address out tri-stated not defined data port tri-stated tri-stated peripheral i/o tri-stated tri-stated register reset power down mode pmmr0 & 1 cleared (power up reset) unchanged unchanged (warm reset) micro ? cells flip-flop unchanged* unchanged* all other registers cleared to ? unchanged table 30. chip status during reset and power down mode other features (cont.) * the micro ? cell flip-flop can be cleared or set by the reset input or the pdn (power down) signal, depending on the .re and .pr equations that are defined in the psdabel file. security protection the psd813fn/fh has a programmable security bit which acts as a duplication barrier. when the bit is set, the contents of the flash and boot eprom, non-volatile configuration bits, and the plds cannot be read by device programmers. the security bit is set through the psdsoft software and is embedded in the compiled output file. the security bit is uv erasable and a secured windowed part can be erased and re-programmed.
preliminary psd813fn/fh 51 symbol parameter condition min max unit t stg storage temperature cldcc ?65 + 150 ? pldcc ?65 + 125 ? commercial 0 + 70 ? operating temperature industrial ?40 + 85 ? military ?55 + 125 ? voltage on any pin with respect to gnd ?0.6 + 7 v v pp programming supply voltage with respect to gnd ?0.6 + 14 v v cc supply voltage with respect to gnd ?0.6 + 7 v esd protection > 2000 v absolute maximum ratings note: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. range temperature v cc v cc tolerance -15 commercial 0 c to +70? + 5 v 10% symbol parameter condition min typ max unit v cc supply voltage all speeds 4.5 5 5.5 v operating range recommended operating conditions
psd813fn/fh preliminary 52 ac/dc parameters the following tables describe the ad/dc parameters of the psd813fn/fh: o dc electrical specification o ac timing specification pld timing combinatorial timing synchronous clock mode asynchronous clock mode input micro ? cell timing microcontroller timing read timing write timing peripheral mode timing power down and reset timing following are some issues concerning the parameters presented: o in the dc specification the supply current is given for different modes of operation. before calculating the total power consumption, determine the percentage of time that the psd813fn/fh is in each mode. also the supply power is considerably different if cmiser is "on". o the ac power component gives the pld, eprom, and sram ma/mhz specification. o in the mcu timing specification add the required time delay when cmiser is "on".
preliminary psd813fn/fh 53 notes: 1. reset input has hysteresis. v il1 is valid at or below .2v cc ?1. v ih1 is valid at or above .8v cc . 2. csi deselected or internal pd is active. 3. sleep mode bit is set and internal pd is active. 4. i out = 0 ma. symbol parameter conditions min typ max unit v cc supply voltage all speeds 4.5 5 5.5 v v ih high level input voltage 4.5 v < v cc < 5.5 v 2 v cc +.5 v v il low level input voltage 4.5 v < v cc < 5.5 v 0.5 0.8 v v ih1 reset high level input voltage (note 1) .8 v cc v cc +.5 v v il1 reset low level input voltage (note 1) ?5 .2 v cc ?1 v v hys reset pin hysteresis 0.3 v v ol output low voltage i ol = 20 ?, v cc = 4.5 v 0.01 0.1 v i ol = 8 ma , v cc = 4.5 v 0.15 0.45 v v oh output high voltage i oh = 20 ?, v cc = 4.5 v 4.4 4.49 v except vbaton, ceout i oh = 2 ma , v cc = 4.5 v 2.4 3.9 v v sby sram standby voltage 2.0 v cc v i sby sram standby current v cc = 0 v 0.5 1 a i idle idle current (v stby pin) v cc > v sby 0.1 0.1 ? v df sram data retention voltage only on v stby 2v i sb standby supply power down mode csi >v cc ?3 v (note 2) 50 100 ? current sleep mode csi >v cc ?3 v (note 3) 25 50 ? i li input leakage current v ss < v in > v cc ? ?1 1 a i lo output leakage current .45 < v in > v cc ?0 5 10 ? pld only f = 0 mhz 400 700 ?/pt cmiser = on 00 ma and not selected eprom adder cmiser = on and eprom selected (x8 data bus) 10 15 ma cmiser = off 15 20 ma i cc (dc) operating during flash read, 10 18 ma (note 4) supply current f = 0 mhz flash dc adder during flash erase/write, 25 50 ma f = 0 mhz sram not selected 0 0 ma sram adder cmiser = on, sram selected (x8 data bus) 25 40 ma cmiser = off 15 20 ma pld 2 3 ma/mhz i cc (ac) eprom or sram 2 ma/mhz flash ac adder 2 ma/mhz dc characteristics (5 v 10% versions)
psd813fn/fh preliminary 54 psd813fn/fh ac/dc parameters ? gpld and ecspld timing (5 v 10% versions) -15 pt slew symbol parameter conditions min max aloc rate unit t pd1 ecspld input pin to ecspld (notes 1 & 2) 24 add 3 ns combinatorial output gpld input pin/feedback to gpld t pd2 combinatorial output port c (note 2a) 32 add 2 ns gpld input pin/feedback to gpld t pd3 combinatorial output port a or b (note 2a) 34 ns gpld input to ecspld output enable (notes 2 & 2a) 29 add 3 ns t ea gpld input to gpld output enable (notes 2a & 2b) 32 ns gpld input to ecspld output disable (notes 2 & 2a) 29 add 3 ns t er gpld input to gpld output disable (notes 2a & 2b) 32 ns t arp gpld register clear or preset delay (notes 2a & 2b) 33 ns t arpw gpld register clear or preset (notes 2a & 2b) 29 ns pulse width t ard gpld array delay any micro ? cell 22 add 2 ns gpld and ecspld combinatorial timing (5 v 10%) notes: 1. ecspld input pins are a(0:15), pgr(0:3), cntl(0:2), pdn. 2. ecspld outputs are pa(0:3), pb(0:3), pd(0:2). 2a. gpld inputs are a(0:15), pgr(0:3), cntl(0:2), pa(0:7), pb(0:7), pc(0:7), pd(0:2), ale, pdn. add 25ns for propagation delay from rstin pin. 2b. gpld outputs are pa(4:7), pb(4:7), pc(0:7).
preliminary psd813fn/fh 55 psd813fn/fh ac/dc parameters ? gpld and ecspld timing (5 v 10% versions) -15 pt slew symbol parameter conditions min max aloc rate unit maximum frequency external feedback 1/(t s + t co ) 25.00 mhz maximum frequency internal 1/(t s + t co ?0) 31.25 mhz f max feedback (f cnt ) maximum frequency pipelined data 1/(t ch + t cl ) 35.71 mhz t s input setup time (note 2a) 20 add 2 ns t h input hold time (note 2a) 0 ns t ch clock high time clock input 15 ns t cl clock low time clock input 15 ns t co clock to output delay clock input 22 ns t ard gpld array delay any micro ? cell 22 add 2 ns t min minimum clock period t ch + t cl 29 ns gpld micro ? cell synchronous clock mode timing (5 v 10% ) note: 2a. gpld inputs are a(0:15), pgr(0:3), cntl(0:2), pa(0:7), pb(0:7), pc(0:7), pd(0:2), ale, pdn. add 25ns for propagation delay from rstin pin. -15 pt slew symbol parameter conditions min max aloc rate unit maximum frequency external feedback 1/(t sa + t coa ) 21.74 mhz maximum frequency internal 1/(t sa + t coa ?0) 27.78 mhz f maxa feedback (f cnta ) maximum frequency pipelined data 1/(t ch + t cl ) 35.71 mhz t sa input setup time (note 2a) 12 add 2 ns t ha input hold time (note 2a) 12 ns t cha clock input high time (note 2a) 15 ns t cla clock input low time (note 2a) 15 ns t coa clock to output delay (note 2a) 37 ns t ard gpld array delay any micro ? cell 22 add 2 ns t mina minimum clock period 1/ f cnta 43 ns gpld micro ? cell asynchronous clock mode timing (5 v 10%)
psd813fn/fh preliminary 56 -15 pt symbol parameter conditions min max aloc unit t is input setup time (note 2c) 0 ns t ih input hold time (note 2c) 26 ns t inh nib input high time (note 2c) 18 ns t in l nib input low time (note 2c) 18 ns t ino nib input to combinatorial output delay (note 2c) 59 add 2 ns input micro ? cell timing (5 v 10%) notes: 2c. inputs from port a, b and c relative to register/latch clock from the pld. ale latch timings refer to t avlx and t lxax . psd813fn/fh ac/dc parameters ? gpld and ecspld timing (5 v 10% versions)
preliminary psd813fn/fh 57 explanation of ac symbols for pld timing. example: t avlx ? time from address valid to ale invalid. signal letters a address input c ceout output d input data e e input g internal wdog_on signal i interrupt input l ale input n reset input or output p port signal output q output data r wr, uds, lds, ds, iord, psen inputs s chip select input t r/w input w internal pdn signal b vstby output m output micro ? cell signal behavior t time l logic level low or ale h logic level high v valid x no longer a valid logic level z float pw pulse width microcontroller interface ac/dc parameters (5v 10% versions)
psd813fn/fh preliminary 58 -15 cmiser symbol parameter conditions min max on unit t lvlx ale or as pulse width 28 0 ns t avlx address setup time (note 4) 10 0 ns t lxax address hold time (note 4) 11 0 ns t avqv address valid to data valid (note 4) 150 add 10 ns t slqv cs valid to data valid 150 add 10 ns rd to data valid 8/16-bit bus (note 3) 40 0 ns t rlqv rd to data valid 8-bit bus, 8031 separate mode (note 3a) 45 0 ns t rhqx rd data hold time (note 3) 0 0 ns t rlrh rd pulse width (note 3) 38 0 ns t rhqz rd to data high-z (note 3) 33 0 ns t ehel e pulse width 38 0 ns t theh r/w setup time to enable 18 0 ns t eltl r/w hold time after enable 0 0 ns t avpv address input valid to address output delay (note 5) 48 0 ns read timing microcontroller interface ? ac/dc parameters notes: 3. rd timing has the same timing as ds, lds, uds, psen (in 8031 combined mode) signals. 3a. rd and psen have the same timing for 8031 separate mode. 4. any input used to select an internal psd813fn/fh function. 5. in multiplexed mode latched address generated from adio delay to address output on any port.
preliminary psd813fn/fh 59 microcontroller interface ? ac/dc parameters (5 v 10% versions) -15 eprom_cmiser symbol parameter conditions min max on unit t lvlx ale or as pulse width 28 ns t avlx address setup time (note 6) 10 ns t lxax address hold time (note 6) 11 ns t avwl address valid to leading edge of wr (notes 6 and 8) 30 ns t slwl cs valid to leading edge of wr (note 8) 35 ns t dvwh wr data setup time (note 8) 22 ns t whdx wr data hold time (note 8) 5 ns t wlwh wr pulse width (note 8) 28 ns t whax trailing edge of wr to address invalid (note 8) 0 ns t whpv trailing edge of wr to port output valid (note 8) 38 ns address input valid to in 8-bit data bus 48 ns t avpv address output delay mode (note 7) byte programming operation also includes t whwh1 preprogramming time 14 ? t whwh2 sector erase operation not 100% tested 2.2 sec t vcs v cc set up time 50 ? write/erase/program timing (5 v 10%) note: 6. any input used to select an internal psd813fn/fh function. 7. in multiplexed mode latched address generated from adio delay to address output on any port. 8. wr timing has the same timing as e and ds signals.
psd813fn/fh preliminary 60 microcontroller interface ? ac/dc parameters -15 symbol parameter conditions min max unit t avqv (pa) address valid to data valid (note 9) 62 ns t slqv (pa) cs valid to data valid 62 ns rd to data valid (notes 3, 10) 40 ns t rlqv (pa) rd to data valid 8031 mode 45 ns t dvqv (pa) data in to data out valid 26 ns t qxrh (pa) rd data hold time (note 3) 0 ns t rlrh (pa) rd pulse width (note 3) 38 ns t rhqz (pa) rd to data high-z (note 3) 33 ns port a peripheral data mode read timing -15 symbol parameter conditions min max unit t wlqv (pa) wr to data propagation delay (note 8) 35 ns t dvqv (pa) data to port a data propagation delay (note 11) 26 ns t whqz (pa) wr invalid to port a tri-state (note 8) 33 ns port a peripheral data mode write timing notes: 9. any input used to select port a data peripheral mode. 10. data is already stable on port a. 11. data stable on adio pins to data on port a.
preliminary psd813fn/fh 61 microcontroller interface ? ac/dc parameters -15 symbol parameter conditions min max unit t lvdv ale access time from power down 150 ns t lvdv1 ale or csi access time from sleep 200 ns gpld and ecspld propagation delay t pd4 in sleep mode 600 ns t pd5 gpld and ecspld recovery time after sleep mode 250 ns maximum delay from apd enable t clwh to internal pdn valid signal using clkin input 15* t min (?) ? power down timing symbol parameter conditions min typ max unit t nlnh reset active low time 150 ns t opr reset high to operational device 120 ns reset timing
psd813fn/fh preliminary 62 figure 23. read timing t avlx t lxax t lvlx t avqv t slqv t rlqv t rhqx trhqz t eltl t ehel t rlrh t theh t avpv address valid address valid data valid data valid address out ale /as a/d multiplexed bus address non-multiplexed bus data non-multiplexed bus csi rd (psen, ds) (lds, uds) e r/w * t avlx and t lxax are not required for 80c251 in page mode or 80c51xa in burst mode.
preliminary psd813fn/fh 63 figure 24. write timing t avlx t lxax t lvlx t avwl t slwl t whdx t whax t eltl t ehel t wlmv t wlwh t dvwh t theh t avpv address valid address valid data valid data valid address out t whpv standard mcu i/o out ale/as a/d multiplexed bus address non-multiplexed bus data non-multiplexed bus csi wr (ds) e r/ w
psd813fn/fh preliminary 64 figure 26. peripheral i/o write timing figure 25. peripheral i/o read timing t qxrh ( pa) t rlqv ( pa) t rlrh ( pa) t dvqv ( pa) t rhqz ( pa) t slqv ( pa) t avqv ( pa) address data valid ale /as a /d bus rd data on port a csi tdvqv (pa) twlqv (pa) twhqz (pa) address data out a /d bus wr port a data out ale /as
preliminary psd813fn/fh 65 figure 27. combinatorial timing ? pld tpd1 tpd2 tpd3 gpld input external cs output gpld output ecspld input figure 28. synchronous clock mode timing ? pld t ch t cl t co t h t s clkin input registered output
psd813fn/fh preliminary 66 figure 29. asynchronous clock mode timing (product-term clock) figure 30. input micro ? cell timing (product-term clock) tcha tcla tcoa tha tsa clock input registered output t inh t inl t ino t ih t is pt clock input output
preliminary psd813fn/fh 67 figure 31. input to output disable / enable figure 32. asynchronous reset / preset ter tea input input to output enable/disable tarp register output tarpw reset/preset input
psd813fn/fh preliminary 68 figure 33. reset timing figure 34. key to switching waveforms t nlnh t opr waveforms inputs outputs steady input may change from hi to lo may change from lo to hi don't care outputs only steady output will be changing from hi to lo will be changing lo to hi changing, state unknown center line is tri-state
preliminary psd813fn/fh 69 symbol parameter 1 conditions typical 2 max unit c in capacitance (for input pins only) v in = 0 v 4 6 pf c out capacitance (for input/output pins) v out = 0 v 8 12 pf c vpp capacitance (for wr/v pp or r/w/v pp )v pp = 0 v 18 25 pf notes: 1. these parameters are only sampled and are not 100% tested. 2. typical values are for t a = 25? and nominal supply voltages. t a = 25 ?, f = 1 mhz pin capacitance figure 35. ac testing input/output waveform figure 36. ac testing load circuit 3.0v 0v test point 1.5v device under test 2.01 v 195 w c l = 30 pf (including scope and jig capacitance)
psd813fn/fh preliminary 70 psd813fn/fh pin assignments pin no. pin assignments pin no. pin assignments 52-pin 52-pin 52-pin 52-pin pldcc pldcc pldcc pldcc 1 gnd 27 pa2 2 pb5 28 pa1 3 pb4 29 pa0 4 pb3 30 ad0 5 pb2 31 ad1 6 pb1 32 ad2 7 pb0 33 ad3 8 pd2 34 ad4 9 pd1 35 ad5 10 pd0 36 ad6 11 pc7 (csf) 37 ad7 12 pc6 (a18f) 38 v cc 13 pc5 (a17f) 39 a8 14 pc4 (a16f) 40 a9 15 v cc 41 a10 16 gnd 42 a11 17 pc3 (a14f) 43 a12 18 pc2 (vstby) 44 a13 19 pc1 (rdf) 45 a14 20 pc0 (wrf) 46 a15 21 pa7 47 cntl0 22 pa6 48 rst 23 pa5 49 cntl2 24 pa4 50 cntl1 25 pa3 51 pb7 26 gnd 52 pb6
preliminary psd813fn/fh 71 psd813fn/fh package information 46 45 44 43 42 41 40 39 38 37 36 35 34 a15 a14 a13 a12 a11 a10 v cc v cc a8 a9 ad7 ad6 ad5 ad4 pd2 pd1 pd0 pc7 (csf) pc6 (a18f) pc5 (a17f) pc4 (a16f) gnd pc3 (a14f) pc2 (vstby) pc1 (rdf) pc0 (wrf) 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 765432 1 52 51 50 49 48 47 pb0 pb1 pb2 pb3 pb4 pb5 gnd pb6 pb7 cntl1 cntl2 rst cntl0 pa7 pa6 pa5 pa4 pa3 gnd pa2 pa1 pa0 ad0 ad1 ad2 ad3 figure 37. drawing j7 ? 52-pin plastic leaded chip carrier (pldcc) (package type j)
psd813fn/fh preliminary 72 family: plastic leaded chip carrier millimeters inches symbol min max notes min max notes a 4.19 4.57 0.165 0.180 a1 2.54 2.79 0.100 0.110 a2 3.66 3.86 0.144 0.152 b 0.33 0.53 0.013 0.021 b1 0.66 0.81 0.026 0.032 c 0.246 0.261 0.0097 0.0103 d 19.94 20.19 0.785 0.795 d1 19.05 19.15 0.750 0.754 d2 17.53 18.54 0.690 0.730 d3 15.24 reference 0.600 reference e 19.94 20.19 0.785 0.795 e1 19.05 19.15 0.750 0.754 e2 17.53 18.54 0.690 0.730 e3 15.24 reference 0.600 reference e1 1.27 reference 0.050 reference n52 52 020197r1 figure 37a. drawing j7 ? 52-pin plastic leaded chip carrier (pldcc) (package type j) e1 e 52 51 1 2 3 d1 d view a r .025 .045 d3 b1 b a1 a d2 a2 c e3 e1 view a e2
preliminary psd813fn/fh 73 appendix a ? flash memory description the psd813fn/fh has a non-volatile flash memory that may be erased electrically at the sector level, and programmed byte-by-byte. organization the flash memory organization is 512k x 8 bits (only 128k x 8 is used) with address lines a0 a18 and data inputs/outputs d0 d7. memory control is provided by chip enable (csf), output enable (rdf) and write enable (wrf) inputs. erase and program are performed using embedded algorithms through the internal program/erase controller (p/e.c.). data output bits d7 and d6 provide polling or toggle signals during automatic program or erase to indicate the ready/busy state of the internal program/erase controller. sectors erasure of the memory is in sectors. there are 8 sectors of 64k bytes each in the memory address space. erasure of each sector takes typically 1.5 seconds and each sector can be programmed and erased over 100,000 cycles. sector erasure may be suspended, while data is read from other blocks of the memory, and then resumed. bus operations five operations can be performed by the appropriate bus cycles: read array, read electronic signature, output disable, standby, and write the command of an instruction. command interface command bytes can be written to a command interface (c.i.) latch to perform reading (from the array or electronic signature), erasure or programming. for added data protection, command execution starts after 4 or 6 command cycles. the first, second, fourth and fifth cycles are used to input a code sequence to the command interface. this sequence is equal for all p/e.c. instructions. the command itself and its confirmation ?if it applies are given on the third and fourth or sixth cycles. instructions seven instructions are defined to perform reset, read electronic signature, auto program, sector auto erase, auto bulk erase, sector erase suspend and sector erase resume. the internal program/erase controller (p/e.c.) handles all timing and verification of the program and erase instructions and provides data polling, toggle, and status data to indicate completion of program and erase operations. instructions are composed of up to six cycles. the first two cycles input a code sequence to the command interface which is common to all p/e.c. instructions (see table 4 for command descriptions). the third cycle inputs the instruction set up command instruction to the command interface. subsequent cycles output signature or the addressed data for read operations. for added data protection, the instructions for program and sector or bulk erase require further command inputs. for a program instruction, the fourth command cycle inputs the address and data to be programmed. for an erase instruction (sector or bulk), the fourth and fifth cycles input a further code sequence before the erase confirm command on the sixth cycle. byte programming takes typically 10? while erase is performed in typically 1.5 seconds. erasure of a memory sector may be suspended, in order to read data from another sector, and then resumed. data polling, toggle and error data may be read at any time, including during the programming or erase cycles, to monitor the progress of the operation. when power is first applied or if v cc falls below v lko , the command interface is reset to read array.
psd813fn/fh preliminary 74 operation csf rdf wrf d0 ?d7 read v il v il v ih data output write v il v ih v il data input output disable v il v ih v ih hi-z standby v ih x x hi-z appendix a ? flash memory (cont.) operation csf rdf wrf a0 a1 a6 addresses d0 d7 manufact. code v il v il v ih v il v il v il don? care 20h device code v il v il v ih v ih v il v il don? care 0e2h table 1. operations table 2. electronic signature note: see rsig instruction device operation signal descriptions o a0 ?a18 address inputs the address inputs for the memory array are latched during a write operation. when a0, a1 and a6 are low, the electronic signature manufacturer code is read. when a0 is high and a1 and a6 are low, the device code is read. see the rsig instruction and table 2. o d0 ?d7 data input/outputs the data input is a byte to be programmed or a command written to the c.i. both are latched when chip enable csf and write enable wrf are active. the data output is from the memory array, the electronic signature, the data polling bit (d7), the toggle bit (d6), the error bit (d5) or the erase timer bit (d3). outputs are valid when chip enable csf and output enable rdf are active. the output is high impedance when the chip is deselected or the outputs are disabled. o csf chip enable the chip enable activates the memory control logic, input buffers, decoders and sense amplifiers. csf high deselects the memory and reduces the power consumption to the standby level. csf can also be used to control writing to the command register and to the memory array, while wrf remains at a low level. addresses are then latched on the falling edge of csf while data is latched on the rising edge of csf. o rdf output enable the output enable gates the outputs through the data buffers during a read operation. o wrf write enable this input controls writing to the command register and address and data latches. addresses are latched on the falling edge of wrf, and data inputs are latched on the rising edge of wrf. o v cc supply voltage the power supply for all operations (read, program and erase). o v ss ground v ss is the reference for all voltage measurements. note: x = v il or v ih .
preliminary psd813fn/fh 75 mne. instr. cyc. 1st cyc. 2nd cyc. 3rd cyc. 4th cyc. 5th cyc. 6th cyc. 7th cyc. rst (3,8) reset 1+ addr. (2,0) x read memory array until a new write cycle is initiated. data 0f0h rsig (3) read 3+ addr. (2,5) x5555h x2aaah x5555h read electronic signature until a new data 0aah 55h 90h write cycle is initiated. see note 4. addr. (2,5) x5555h x2aaah x5555h program address read data polling or toggle pg program 4 data 0aah 55h 0a0h program bit until program completes. data se sector 6 addr. (2,5) x5555h x2aaah x5555h x2aaah x2aaah sector additional erase address sector (6) data 0aah 55h 80h 0aah 55h 30h 30h be bulk 6 addr. (2,5) x5555h x2aaah x5555h x5555h x2aaah x5555h note 7 erase data 0aah 55h 80h 0aah 55h 10h es erase 1 addr. (2,5) x read until toggle stops, then read all the data needed from any suspend data 0b0h sector(s) not being erased then resume erase. er erase 1 addr. (2,5) x read data polling or toggle bit until erase completes or erase resume data 30h is suspended another time. table 3. instructions (note 1) notes: 1. command not interpreted in this table will default to read array mode. 2. x = don? care. 3. the first cycle of the rst, rsp or rsig instruction is followed by read operations to read memory array, status register or electronic signature codes. any number of read cycles can occur after one command cycle. 4. signature address bits a0, a1, a6 at v il will output manufacturer code (20h). address bits a0 at v ih and a1, a6 at v il will output device code (0e2h). 5. address bits a16, a17, a18 are don? care for coded address inputs. 6. optional, additional sectors addresses must be entered within a 80? delay after last write entry, timeout status can be veri fied through d3 value. when full command is entered, read data polling or toggle bit until erase is completed or suspended. 7. read data polling or toggle bit until erase completes. 8. a wait time of 5? is necessary after a reset command before starting any operation. device operation (cont.) hex code command 00h invalid/reserved 10h bulk erase confirm 30h sector erase resume/confirm 80h set-up erase 90h read electronic signature 0a0h program 0b0h erase suspend 0f0h reset table 4. commands
psd813fn/fh preliminary 76 dq name logic level definition note ? erase complete indicates the p/e.c. status, check during 7 data ? erase on going program or erase, and on completion polling dq program complete before checking bits d5 for program or dq program on going erase success. ?1-0-1-0-1-0-1- erase or program on successive read output complementary data going on d6 while programming or erase operations 6 toggle bit ?0-0-0-0-0-0-0- program (??on d6) are going on. d6 remain at constant level when complete p/e.c. operations are completed or erase ?1-1-1-1-1-1-1- erase or program suspend is acknowledged. (??on d6) complete ? program or erase error this bit is set to ??if p/e.c. has exceeded the 5 error bit ? program or erase on specified time limits. going 4 ? ? ? erase timeout period p/e.c. erase operation has started. only 3 erase expired possible command entry is erase suspend time bit ? erase timeout period (es). an additional sector to be erased in on going parallel can be entered to the p/e.c. 2 reserved 1 reserved 0 reserved note: logic level ??is high, ??is low. -0-1-0-0-0-1-1-1-0- represent bit value in successive read operations. table 5. status register device operation (cont.)
preliminary psd813fn/fh 77 device operation (cont.) memory sectors the sectors of the flash memory are shown in figure 1. the memory array is divided into 8 sectors of 64k bytes. each sector can be erased separately or any combination of sectors can be erased simultaneously. the sector erase operation is managed automatically by the p/e.c. the operation can be suspended in order to read from any another sector, and then resumed. operations operations are defined as specific bus cycles and signals which allow memory read, command write, output disable, standby, read status bits, and electronic signature read. they are shown in tables 1 and 2. o read read operations are used to output the contents of the memory array, the status register or the electronic signature. both chip enable csf and output enable rdf must be low in order to read the output of the memory. the chip enable input also provides power control and should be used for device selection. output enable should be used to gate data onto the output independent of the device selection. the data read depends on the previous command written to the memory (see instructions rst and rsig, and status bits). o write write operations are used to give instruction commands to the memory or to latch input data to be programmed. a write operation is initiated when chip enable csf is low and write enable wrf is low with output enable rdf high. addresses are latched on the falling edge of wrf or csf whichever occurs last. commands and input data are latched on the rising edge of wrf or csf whichever occurs first. o output disable the data outputs are high impedance when the output enable rdf is high with write enable wrf high. o standby the memory is in standby when chip enable csf is high and program/erase controller p/e.c. is idle. the power consumption is reduced to the standby level and the outputs are high impedance, independent of the output enable rdf or write enable wrf inputs. o automatic standby after 150 ns of inactivity and when cmos levels are driving the addresses, the chip automatically enters a pseudo standby mode where power consumption is reduced to the cmos standby value, while outputs are still driving the bus. appendix a ? flash memory (cont.)
psd813fn/fh preliminary 78 instructions and commands the command interface (c.i.) latches commands written to the memory. instructions are made up from one or more commands to perform reset, read electronic signature, sector erase, bulk erase, program, sector erase suspend and erase resume. commands are made of address and data sequences. addresses are latched on the falling edge of wrf or csf and data is latched on the rising of wrf or csf. the instructions require from 1 to 6 cycles, the first or first three of which are always write operations used to initiate the command. they are followed by either further write cycles to confirm the first command or execute the command immediately. command sequencing must be followed exactly. any invalid combination of commands will reset the device to read array. the increased number of cycles has been chosen to assure maximum data security. commands are initial- ized by two preceding coded cycles which unlock the command interface. in addition, for erase, command confirmation is again preceded by the two coded cycles. p/e.c. status is indicated during command execution by data polling on d7, detection of toggle on d6, or error on d5 and erase timer d3 bits. any read attempt during program or erase command execution will automatically output those four bits. the p/e.c. automatically sets bits d3, d5, d6 and d7. other bits (d0, d1, d2 and d4) are reserved for future use and should be masked. o data polling bit dq7 when programming operations are in progress, this bit outputs the complement of the bit being programmed on d7. during erase operation, it outputs a ?? after completion of the operation, d7 will output the bit last programmed or a ??after erasing. data polling is valid only effective during p/e.c. operation, that is after the fourth wrf pulse for programming or after the sixth wrf pulse for erase. it must be performed at the address being programmed or at an address within the sector being erased. if the byte to be programmed belongs to a protected sector the command is ignored. if all the sectors selected for erasure are protected, d7 will set to ??for about 100 ?, and then return to previous addressed memory data. see figure 2 for the data polling flowchart. appendix a ? flash memory (cont.) a18 1 1 1 1 0 0 0 0 top address 7ffffh 6ffffh 5ffffh 4ffffh 3ffffh 2ffffh 1ffffh 0ffffh bottom address 70000h 60000h 50000h 40000h 30000h 20000h 10000h 00000h a17 1 1 0 0 1 1 0 0 a16 1 0 1 0 1 0 1 0 64k bytes sector 64k bytes sector 64k bytes sector 64k bytes sector 64k bytes sector figure 1. memory map and sector address table
preliminary psd813fn/fh 79 appendix a ? flash memory (cont.) start read d5 & d7 at valid address yes yes yes no no no d7 = data d5 =1 d7 = data read d7 fail pass figure 2. data polling flowchart instructions and commands (cont.) o toggle bit d6 when programming operations are in progress, successive attempts to read d6 will output complementary data. d6 will toggle following toggling of either rdf or csf when rdf is low. the operation is completed when two successive reads yield the same output data. the next read will output the bit last programmed or a ??after erasing. the toggle bit is valid only effective during p/e.c. operations, that is after the fourth wrf pulse for programming or after the sixth wrf pulse for erase. if the byte to be programmed belongs to a protected sector the command will be ignored. if the sectors selected for erasure are protected, d6 will toggle for about 100 ? and then return back to read. see figure 3 for toggle bit flowchart and figure 4 for toggle bit waveforms.
psd813fn/fh preliminary 80 appendix a ? flash memory (cont.) start read d5 & d6 no yes no yes yes no d6 = toggle d5 =1 d6 = toggle read d6 fail pass figure 3. data toggle flowchart a0 -a18 csf rdf wrf d6 d0-d5, d7 last cycle of program of erase data toggle read cycle data toggle read cycle read cycle valid valid valid stop toggle ignore trlqv tslqv tavqv figure 4. data toggle d6 ac waveforms
preliminary psd813fn/fh 81 device operation (cont.) instructions and commands (cont.) o error bit d5 this bit is set to ??by the p/e.c. when there is a failure of byte programming, sector erase, or bulk erase that results in invalid data being programmed in the memory sector. in case of error in sector erase or byte program, the sector in which the error occurred or to which the programmed byte belongs, must be discarded. other sectors may still be used. error bit resets after reset (rst) instruction. in case of success, the error bit will set to ??during program or erase and to valid data after write operation is completed. o erase time bit d3 this bit is set to ??by the p/e.c. when the last sector erase command has been entered to the command interface and it is awaiting the erase start. when the wait period is finished, after 80 to 120 ?, d3 returns back to ?? o coded cycles the two coded cycles unlock the command interface. they are followed by a command input or a command confirmation. the coded cycles consist of writing the data 0aah at address 5555h during the first cycle and data 55h at address 2aaah during the second cycle. addresses are latched on the falling edge of wrf or csf while data is latched on the rising edge of wrf or csf. the coded cycles happen on first and second cycles of the command write or on the fourth and fifth cycles. o reset (rst) instruction the reset instruction consists of one write operation giving the command 0f0h. it can be optionally preceded by the two coded cycles. after wait state of 5 ?, subsequent read operations will read the memory array addressed and output the read byte. o read electronic signature (rsig) instruction this instruction uses the two coded cycles followed by one write cycle giving the command 90h to address 5555h for command setup. a subsequent read will output the manufacturer code or the device code depending on the levels of a0, a1, a6, a16, a17 and a18. the manufacturer code, 20h, is output when the addresses lines a0, a1 and a6 are low, the device code, 0e2h is output when a0 is high with a1 and a6 low. see table 2. o bulk erase (be) instruction this instruction uses six write cycles. the erase set-up command 80h is written to address 5555h on third cycle after the two coded cycles. the bulk erase confirm command 10h is written at address 5555h on sixth cycle after another two coded cycles. if the second command given is not an erase confirm or if the coded cycles are wrong, the instruction aborts and the device is reset to read array. it is not necessary to program the array with 00h first as the p/e.c. will automatically do this before erasing to 0ffh. read operations after the sixth rising edge of wrf or csf output the status register bits. during the execution of the erase by the p/e.c. the memory accepts only the reset (rst) command. read of data polling bit d7 return ?? then ??on completion. the toggle bit d6 toggles during erase operation and stops when erase is completed. after completion the status register bit d5 returns a ??if there has been an erase failure because the erasure has not been verified even after the maximum number of erase cycles have been executed. appendix a ? flash memory (cont.)
psd813fn/fh preliminary 82 device operation (cont.) instructions and commands (cont.) o sector erase (se) instruction this instruction uses a minimum of six write cycles. the erase set-up command 80h is written to address 5555h on third cycle after the two coded cycles. the sector erase confirm command 30h is written on sixth cycle after another two coded cycles. during the input of the second command an address within the sector to be erased is given and latched into the memory. additional sector erase confirm commands and sector addresses can be written subsequently to erase other sectors in parallel, without further coded cycles. the erase will start after an erase timeout period of about 100 ?. thus, additional sector erase commands must be given within this delay. the input of a new sector erase command will restart the timeout period. the status of the internal timer can be monitored through the level of d3, if d3 is ??the sector erase command has been given and the timeout is running, if d3 is ?? the timeout has expired and the p/e.c. is erasing the sector(s). before and during erase timeout, any command different from 30h will abort the instruction and reset the device to read array mode. it is not necessary to program the sector with 00h as the p/e.c. will do this automatically before to erasing to 0ffh. read operations after the sixth rising edge of wrf or csf output the status register status bits. during the execution of the erase by the p/e.c., the memory accepts only the es (erase suspend) and rst (reset) instructions. data polling bit d7 returns a ??while the erasure is in progress and a ??when it has completed. the toggle bit d6 toggles during the erase operation. it stops when erase is completed. after completion the status register bit d5 returns ??if there has been an erase failure because erasure has not completed even after the maximum number of erase cycles have been executed. in this case, it will be necessary to input a reset (rst) to the command interface in order to reset the p/e.c. o program (pg) instruction this instruction uses four write cycles. the program command a0h is written on the third cycle after two coded cycles. a fourth write operation latches the address on the falling edge of wrf or csf and the data to be written on its rising edge and starts the p/e.c. during the execution of the program by the p/e.c. by the p/e.c., the memory will not accept any instruction. read operations output the status bits after the programming has started. memory programming is made only by writing ??in place of ??in a byte. o erase suspend (es) instruction the sector erase operation may be suspended by this instruction which consists of writing the command 0b0h without any specific address code. no coded cycles are required. it allows reading of data from another sector while erase is in progress. erase suspend is accepted only during the sector erase instruction execution and defaults to read array mode. writing this command during erase timeout will, in addition to suspending the erase, terminate the timeout. the toggle bit d6 stops toggling when the p/e.c. is suspended. toggle bit status must be monitored at an address out of the sector being erased. the toggle bit will stop toggling between 0.1 ? and 15 ? after the erase suspend (es) command has been written. the flash memory will then automatically set to read memory array mode. when erase is suspended, read from sectors being erased will output invalid data, read from sector not being erased is valid. during the suspension the memory will respond only to erase resume (er) and reset (rst) instructions. the rst command will definitively abort erasure and result in invalid data in the sectors being erased. appendix a ? flash memory (cont.)
preliminary psd813fn/fh 83 device operation (cont.) instructions and commands (cont.) o erase resume (er) instruction if an erase suspend instruction was previously executed, the erase operation may be resumed by giving the command 30h, at any address, and without any coded cycles. o programming the memory can be programmed byte-byte. the program sequence is started by the two coded cycles, followed by writing the program command (0a0h) to the command interface. this is followed by writing the address and data byte to the memory. the program/erase controller automatically starts and performs the programming after the fourth write operation. during programming the memory status is checked by reading the status bits d5, d6 and d7 which show the status of the p/e.c. d6 and d7 determine if programming is on going or has completed and d5 allows a check to be made for any possible error. power up the memory command interface is reset on power up to read array. either csf or wrf must be tied to v ih during power-up to allow maximum security and the possibility to write a command on the first rising edge of csf or wrf. any write cycle initiation is blocked when v cc is below v lko . supply rails normal precautions must be taken for supply voltage decoupling. each device in a system should have the v cc rail decoupled with a 0.1 ? capacitor close to the v cc and v ss pins. the pcb trace widths should be sufficient to carry v cc program and erase currents as required. appendix a ? flash memory (cont.) parameter min typ max unit chip program (byte) 6 sec bulk erase (preprogrammed) 2.5 30 sec bulk erase 8.5 sec sector erase (preprogrammed) 1 30 sec sector erase 1.5 sec byte program 10 1200 ? program/erase cycles (per sector) 100,000 cycles table 6. program, erase times and program, erase endurance cycles (t a = 0 to 70?; v cc = 5 v 10% or 5 v 5%) product revision data sheet revisions reason changes original psd813fn/fh initial release (10/97) product revisions return to main menu

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